JPS5818334Y2 - amplifier circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a DC amplifier circuit using transistors, and particularly to an amplifier circuit in which the input bias offset voltage is set to zero volts and the offset voltage at the output terminal is eliminated.

Conventionally, an amplifier circuit in which the input bias offset voltage is set to zero volts has a circuit configuration shown in FIG.

That is, the input source resistor R1 is connected to the input, and is also connected to the base of one transistor Q2 of the PNP transistors Q2 and Q3 constituting the differential amplifier and the collector of the constant current power supply NPN transistor Q1. .

The differential amplifier is connected to a positive power supply via a common emitter resistor R3, and the collector of one transistor Q2 is connected to a negative power supply via a load resistor R4 and to the base of a next-stage amplification transistor Q4. .

The emitter of this amplifying transistor Q4 is connected to a negative power supply through an emitter resistor R6, and the collector is connected to a positive power supply through a load resistor R5, a load RL, and a negative feedback resistor R7t to the base of the transistor Q3 of the differential amplifier through R8. Connected.

The constant current power supply transistor Q1 has a reference power supply E1 at its base.
is connected, and its emitter is connected to a negative power supply via an emitter variable resistor R2.

To explain the operation of the above circuit configuration,
The signal applied from the input is amplified by transistors Q2-Q4, and the amount of feedback determined by the ratio of feedback resistors R7 and R8 is negatively fed back to transistor Q3.

Here, the current amplification factor hFE of transistor Q2 is h F
E,2, its collector current is I2, and the pace current of transistor Q2 is IB2, then IB2
= I2/hFE2.

When this current flows through the resistor R1, the base voltage of the transistor Q2 becomes VB2IB2×R1, where B is the base voltage of the transistor Q2.
When the gain of this amplifier is G, an input bias offset voltage vB generates a voltage VBXG as an output offset voltage across the load RL.

That is, it is necessary to prevent the base current of the transistor Q2 from flowing through the resistor R1.

For this purpose, the emitter variable resistor is adjusted so that the base current IB of the transistor Q2 and the collector current of the constant current source transistor Q1 are made equal.

However, since the transistor Q2 is in the first stage, its collector current 2 is not very large, and its base current IB2 is also small.

The collector current of the constant current power transistor Q1 selected to be equal to the base current IB2 is also small, and therefore the base current of the constant current power transistor Q1 is further reduced.

As a result, this constant current power supply transistor Q1 is used near the cutoff region, and the emitter variable resistor R
2, it is extremely difficult to adjust the minute current.

Furthermore, since one is a base current and the other is a collector current, the amount of change in each current due to external influences such as temperature is different, and as a result, there is a very high possibility that an offset voltage will occur.

Therefore, the present invention has been devised to eliminate the above-mentioned drawbacks, and aims to provide an amplifier that is stable even against external fluctuations such as temperature and can easily obtain an input/output offset voltage of zero volts.

Hereinafter, the present invention will be explained in detail using FIG. 2.

The same parts as in Fig. 1 are indicated by the same symbols, but the collector of the NPN transistor Q1 is connected to the positive power supply, its base is connected to the base of the transistor Q2, and the emitter is connected to the negative power supply via the emitter variable resistor R2. be done.

By forming the circuit configuration as described above, transistor Q2
base current IB2 and base current I of upper transistor Q1
The emitter variable resistor R2 is adjusted so that B2 becomes equal.

If properly adjusted, the base current of transistor Q2 will become the base current of transistor Q1 since transistors Q2 and Ql are transistors of different conductivity types.

Therefore, even with changes in external temperature, etc., the base currents change to the same degree, so an amplifier with a stable offset voltage of zero can be obtained.

Further, since the transistor Q1 is connected as an emitter follower, the input impedance can be arbitrarily selected.

Further, even if the temperature change rates of the current amplification factors hFE of the transistors Q□ and Q2 are different from each other, the difference can be corrected by replacing it with a change in the power supply voltage.

For example, if the change in the current amplification factor hFF of the transistor Q1 is larger than that of the transistor Q2, IBI<IB2 due to the temperature rise.

At this time, if the voltage of the negative power supply -B is increased, the collector current of the transistor Q1 will increase, and the base current IBI will also increase, so it is possible to correct IBI'''IB2 by changing the voltage of the negative power supply -B, and the input It is possible to prevent output offset from occurring.

In the above embodiment, a balanced differential amplifier is used as the first-stage amplification amplifier, one transistor is used as the first-stage DC amplification transistor, and negative feedback is applied to the other transistor, but this is not necessarily the case. It is not necessary that the first stage amplifier is an unbalanced type, but the present invention can be equally applied as long as the input bias offset voltage is generated by the base current flowing through the bias resistor.

As explained above, the present invention can achieve many of the above-mentioned effects without increasing the number of parts compared to the prior art, and when used in an input capacitorless DC amplifier, its electrical performance can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 shows a conventional amplifier circuit, and FIG. 2 shows an amplifier circuit according to an embodiment of the present invention. Q1-Q3...Transistor, RL...
·load.

Claims (1)

[Scope of utility model registration request] An amplifier circuit including a first transistor for initial stage DC amplification, the base of which is connected in common with the base of the first transistor, and the collector of which is connected to the base of the first transistor. a second transistor of a conductivity type different from that of the first transistor connected to a first power source and whose emitter is connected to a second power source via a variable resistor; An amplifier circuit characterized in that the base current of the first transistor and the base current of the second transistor are set to be equal.