JPS6257425U - - Google Patents
Info
- Publication number
- JPS6257425U JPS6257425U JP14731085U JP14731085U JPS6257425U JP S6257425 U JPS6257425 U JP S6257425U JP 14731085 U JP14731085 U JP 14731085U JP 14731085 U JP14731085 U JP 14731085U JP S6257425 U JPS6257425 U JP S6257425U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- differential amplifier
- diode connected
- current mirror
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の電子回路の回路図、第２図は
従来の電子回路の回路図である。
１……差動増幅器、８……カレントミラー回路
、１５……電流増幅器。
FIG. 1 is a circuit diagram of an electronic circuit according to the present invention, and FIG. 2 is a circuit diagram of a conventional electronic circuit. 1...Differential amplifier, 8...Current mirror circuit, 15...Current amplifier.
Claims (1)
ランジスタよりなる差動増幅器と、該差動増幅器
の負荷として接続された、第３のトランジスタと
第４のトランジスタよりなるカレントミラー回路
と、該第１のトランジスタと該第３のトランジス
タとの間に接続された第１のダイオードと、該第
１のトランジスタと該第４のトランジスタとの間
に接続された第２のダイオードとを有することを
特徴とする電子回路。 a differential amplifier consisting of a first transistor and a second transistor connected differentially; a current mirror circuit consisting of a third transistor and a fourth transistor connected as a load of the differential amplifier; A first diode connected between the first transistor and the third transistor, and a second diode connected between the first transistor and the fourth transistor. electronic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14731085U JPH0352031Y2 (en) | 1985-09-26 | 1985-09-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14731085U JPH0352031Y2 (en) | 1985-09-26 | 1985-09-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6257425U true JPS6257425U (en) | 1987-04-09 |
| JPH0352031Y2 JPH0352031Y2 (en) | 1991-11-11 |
Family
ID=31060554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14731085U Expired JPH0352031Y2 (en) | 1985-09-26 | 1985-09-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0352031Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991013491A1 (en) * | 1990-02-21 | 1991-09-05 | Kabushiki Kaisha Sankyo Seiki Seisakusho | Transistor saturation-preventing circuit |
-
1985
- 1985-09-26 JP JP14731085U patent/JPH0352031Y2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991013491A1 (en) * | 1990-02-21 | 1991-09-05 | Kabushiki Kaisha Sankyo Seiki Seisakusho | Transistor saturation-preventing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0352031Y2 (en) | 1991-11-11 |