JPS6261371A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the mutual conductance by reducing the thickness of an electron supply layer only in a region under a gate electrode. CONSTITUTION:An aluminum-indium-arsenic mixed crystal semiconductor buffer layer 2, a gallium-indium-arsenic mixed crystal semiconductor layer 3 are formed on an indium-phosphorus substrate 1. Silicon impurity-added aluminum-indium- arsenic mixed crystal semiconductor layer 4, an N-type impurity-added indium- phosphorus semiconductor layer 5 and an N-type impurity-added aluminum- indium-arsenic mixed crystal semiconductor layer 6 are formed, a 3-layer electron supply layer 7 is formed, and source electrode 8 and drain electrode 9 are formed. The layer 6 is removed with an etchant which mainly contains phosphoric acid with photoresist 10, the layer 5 is removed with an etchant which mainly contains hydrochloric acid, and a gate electrode 11 made of platinum and gold is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor and a method for manufacturing the same.

[Prior art and its problems]

Conventionally, an electron supply layer is provided on an indium/phosphorous substrate and is made of an aluminum/indium/arsenic mixed crystal semiconductor layer with n-type impurities added on a gallium/indium/arsenic mixed crystal semiconductor layer. having a gate electrode on top;
A field effect transistor with source and drain electrodes on both sides has been proposed and prototyped (C-Y
-C11en) Electron Devices and Letters (
I EEEE Electron Device Lett
e s), EDL-3, No. 6, 1982, 152
page). In the field effect transistor, the thickness of the electron supply layer is constant between the source electrode and the drain electrode. However, the field effect transistor has the following problems.

In other words, in order to improve mutual conductance,
It is necessary to thin the electron supply layer in the region below the gate electrode. However, in the prior art, the thickness of the electron supply layer was constant between the source electrode and the drain electrode, so the electron supply layer between the gate electrode and the source electrode had to be made thin as well.

If the electron supply layer in this region is thinned, it becomes difficult to supply a sufficient number of electrons to the two-dimensional electron layer formed in the gallium-indium-arsenic mixed crystal semiconductor layer in contact with the electron supply layer in this region. , this increases the resistance between the source electrode and the gate electrode, that is, the source resistance. The transconductance of a field effect transistor decreases with increasing source resistance. Therefore, in the prior art, even if the electron supply layer is made thinner in order to achieve higher mutual conductance, it is difficult to improve the mutual conductance due to the influence of an increase in source resistance.

In the conventional structure described above, after the entire electron supply layer made of an aluminum indium-arsenic mixed crystal semiconductor is formed to a thickness that does not cause any reduction in the number of two-dimensional electrons, only the region where the gate electrode will be formed is photo-photographed. It was fabricated by exposing the area using phosphorography technology, covering other areas with resist, and thinning this area by etching.

According to this method, the controllability of the thickness of the electron supply layer under the gate electrode is determined by the accuracy of etching.

The accuracy and reproducibility of this etching varies by at most about ±10% depending on the actual value of the electron supply layer. This variation causes large variations in the characteristics of field effect transistors. For example, the final value voltage is approximately IV
It has been difficult to fabricate field-effect transistors with uniform characteristics with good reproducibility using conventional methods.

[Means to solve the problem]

The present invention solves the above problems, and its structure will be explained below using FIG. 1 corresponding to an embodiment. As shown in FIG. 1, in the present invention, a recess is provided in the electron supply layer 7, and a gate electrode 11 is provided in the recess.In order to realize this structure with good reproducibility,
The electron supply layer 7 has a three-layer structure consisting of a first layer 4 of an aluminum/indium/arsenic mixed crystal semiconductor doped with n-type impurities, a second layer 5 of an indium/phosphorous semiconductor, and a third layer 6 of an aluminum/indium/arsenic mixed crystal semiconductor. That is.

A selective etching method was applied to create the structure described above. That is, the third layer of aluminum/indium arsenide mixed crystal semiconductor in the region where the gate electrode is to be formed is removed using an etching solution containing phosphoric acid as a main component, and the second layer of indium/phosphorous semiconductor is removed using an etching solution containing hydrochloric acid as a main component. That's what I do.

[For production]

As mentioned above, in a field effect transistor based on the same operating principle as the field effect transistor according to the invention, the transconductance increases as the electron supply layer under the gate electrode becomes thinner. However, in the field effect transistor according to the present invention as shown in FIG. 1, by thinning the electron supply layer 7 only in the region below the gate electrode 11, mutual conductance is improved and The electron supply layer 7 in the region other than under the gate electrode 11 is made to have a thickness that does not cause a decrease in the number of two-dimensional electrons so that the source resistance does not increase.
Prevents decrease in transconductance due to increase in source resistance.

Hereinafter, a method for manufacturing the structure of the present invention using a selective etching method will be explained. First, as shown in FIG. 2(a), the electron supply layer 7, which conventionally consisted only of an aluminum-indium-arsenic mixed crystal semiconductor, is replaced with an aluminum-indium-O-arsenic mixed-crystal semiconductor layer, a M4 indium-phosphorous semiconductor second layer 5, an aluminum-indium-arsenic mixed crystal semiconductor layer 5, It has a three-layer structure consisting of a third layer 6 of arsenic mixed crystal semiconductor.

Here, the thickness of the electron supply layer is set to a thickness that does not cause a decrease in the number of two-dimensional electrons in all eight layers. Next, as shown in FIG. 2(b), only the region where the gate electrode will be formed is exposed by photolithography, and the other regions are covered with resist 1.
Cover with 0. Then, as shown in FIG. 2(c), the third layer 6 of the aluminum-indium-arsenic mixed crystal semiconductor layer 6 is removed using an etching solution containing phosphoric acid as the main component. Since the etching solution hardly etches the indium-phosphorus semiconductor, it is possible to completely remove only the third layer G of the aluminum-indium-arsenic mixed crystal semiconductor). Next, the indium phosphorus semiconductor second layer 5 is removed using an etching solution containing hydrochloric acid as the main component (here, since the etching solution containing hydrochloric acid as the main component hardly etches the aluminum-indium-arsenic mixed crystal semiconductor, (only the indium-phosphorus semiconductor second layer 5 can be completely removed). When a gate electrode is formed in the recess formed in this way, the thickness of the electron supply layer under the gate electrode is
The thickness is equal to the thickness of the first layer of arsenic mixed crystal semiconductor. A structure (FIG. 2(d)) is obtained.

The field effect transistor according to the present invention is manufactured by metal organic vapor phase epitaxy (MOCVD or OMVPE) or gas source molecular beam epitaxial growth. According to this growth method, the thickness of the grown layer is ±5.
For example, the design value of the thickness of the first layer of aluminum/indium/silicon semiconductor can be controlled within 1%.
・Can be set to 00A. However, in the field effect transistor according to the present invention, the thickness of the electron supply layer under the gate electrode can be controlled within ±5%,
Variations in characteristics can be reduced to 1/3 or less of conventional values.

〔Example〕

An embodiment of the method for manufacturing a field effect transistor according to the present invention will be described below with reference to FIG.

Organometallic decomposition vapor phase growth method (
For example, the aluminum 9 indium arsenide mixed crystal semiconductor buffer layer 2 is grown by using the MOCVD method or OMVPE method) or the gas source molecular beam epitaxial growth method.
．． 5 μm thick, and then a gallium-indium-arsenic mixed crystal semiconductor layer 3 of about 0.5 μm thick is formed. Here, the buffer layer 2 is provided for the purpose of improving the crystallinity of the gallium-indium-arsenic mixed crystal semiconductor layer 3 and preventing impurity diffusion from the substrate 1, and the thickness of the buffer layer 2 may vary depending on the required characteristics. may be a different value. Furthermore, a first layer 4 of an aluminum-indium-arsenic mixed crystal semiconductor to which silicon or the like is added as an n-type impurity in an amount of, for example, about 5×10 an is formed to a thickness of about 40 OA, and then an indium-phosphorous semiconductor layer to which an n-type impurity is added, for example, in an amount of about I x 1018 cm is formed. The second layer 5 is about 100% A1.Finally, the eighth layer 6 of aluminum-indium-arsenic mixed crystal semiconductor doped with an n-type impurity of, for example, 5 x 10"an-3 is about 100%
OA form. Here, the n-type impurity density and layer thickness of the aluminum-indium-e-arsenic mixed crystal semiconductor first layer may be different from the above-mentioned values depending on the design value of the threshold voltage of the field effect transistor.

Next, an ohmic electrode made of, for example, gold, germanium, and nickel is deposited on the electron supply layer 7 and alloyed to form a source electrode 8 and a drain electrode 9. Through the steps up to this point, the structure shown in FIG. 2(a) is obtained.

Next, after coating the entire surface with a photoresist (10T), only the area where the gate electrode will be formed is exposed using photolithography technique as shown in FIG. The aluminum-indium-arsenic mixed crystal semiconductor third layer 6 is removed using a solution, and then the indium-phosphorous semiconductor second layer 7 is removed using an etching solution containing hydrochloric acid as a main component. By making the etching time longer than the time required to completely remove the second layer of indium phosphide semiconductor, a structure as shown in FIG. 2(c) can be obtained. Further, a gate electrode material made of platinum, gold, or the like is deposited, and the resist 10 and unnecessary portions are removed at the same time to form the gate electrode 11.

A vertical cross-sectional view of the field effect transistor completed in this manner is shown in FIG. 2(d).

〔Effect of the invention〕

According to the present invention, it is possible to create a structure in which the electron supply layer in the region below the gate electrode is made thin and the electron supply layer in other regions maintains the required thickness. It can be manufactured with good reproducibility.

[Brief explanation of drawings]

Fig. 1 shows a vertical cross-sectional view of one embodiment of the field effect transistor of the present invention, and Fig. 2 (a), (b), (C
) and (d) show the process of manufacturing a longitudinal cross-sectional view of an embodiment of the present invention. ■... Indium/phosphorous substrate, 2... Aluminum-indium/arsenic mixed crystal semiconductor buffer layer, 3... Gallium-indium/arsenic mixed crystal semiconductor layer, 4... Aluminum/indium/arsenic mixed crystal semiconductor 1st layer, 5... Indium/phosphorous semiconductor second layer, 6... Aluminum/
Indium-arsenic mixed crystal semiconductor third layer, 7... Electron supply layer, 8... Source electrode, 9... Drain electrode, 10
... Photoresist, 11... Gate electrode. 1'+1'- Thousands of amendments November 1985, zf'F3 Mr. Michibe Uga, Commissioner of the Patent Office
, 21, Indication of the case 1985 Patent Application No. 202156g-2, Name of the invention Field-effect transistor and its manufacturing method 3, Person making the amendment Relationship with the case Patent applicant Appointment Kou 15-F Kitahama, Higashi-ku, Osaka-shi Address name (
213) Kawa, President of Sumitomo Electric Industries, Ltd.
Tetsu Yu, Department 4, Agent address: 1-chome Shimaya, Konohana-ku, Osaka [11-3 Sumitomo ↑ Inside 12-Ko Kogyo Co., Ltd. (Telephone: Osaka 461-1031) Name (7881) Patent attorney Tetsu Tsukasa 5, amended Date of order 〆-to 6,
7. Detailed description of the invention and drawings in the amended patent application specification. Contents of amendment] ('l) ``The following 1 in fL:
and correct it. (2) Specification page 7, line 8 1] "Remove 5, (, = 7
- to correct for ``remove here''. (3) 1- is possible on page 7, line 12 of the specification). Correct 1 to [-kotoka deki, otsu), 1. (4) Page 8 of the specification, line 1 [] to line 2 “1: etc. 1-
It will be 7. "of structure" [-also of equal structure C7)-
Correct it to 1. (5) Page 1 () of the specification, line 8 “1,” 1st river (b),
, :ri・[-Figure 2(b)''. (6) Correct the originals of Figures 1 and 2 of the drawings on separate sheets.

Claims (2)

[Claims] (1) It is on an indium-phosphorous substrate and has an electron supply layer made of an aluminum-indium-arsenic mixed crystal semiconductor and an indium-phosphorous semiconductor doped with n-type impurities on a gallium indium-arsenic mixed crystal semiconductor layer. , a gate electrode on the electron supply layer, a source electrode and a drain electrode on both sides of the gate electrode, a recess in which the electron supply layer is thin between the source electrode and the drain electrode, and the recess A field effect transistor characterized in that it has a gate electrode. (2) A first layer of an aluminum-indium-arsenic mixed crystal semiconductor layer on an indium-phosphorus substrate and doped with n-type impurities on a gallium-indium-arsenic mixed-crystal semiconductor layer, a second layer of an indium-phosphorous semiconductor, and aluminum.・An electron supply layer made of a third layer of an indium/arsenic mixed crystal semiconductor is provided, and the third layer of the aluminum/indium arsenide mixed crystal semiconductor in a region where a gate electrode of the electron supply layer is formed is etched with an etching solution containing phosphoric acid as a main component. A method for manufacturing a field effect transistor, comprising: removing the indium-phosphorous semiconductor second layer with an etching solution containing hydrochloric acid as a main component, thereby providing unevenness in the electron supply layer described below.