JPS58173869A - Manufacture of compound semiconductor fet - Google Patents

Abstract

PURPOSE:To manufacture a planar type element with high performance and fine construction by a method wherein N<+> layer, the first and second insulating films are laminated on a semiconductor compound substrate and a hole is opened to form N layer while P<+> type layer of the same or different kind of compound semiconductor is laminated to provide gate electrode thereon. CONSTITUTION:Si3N4 film 13, SiO2 film 14 and resist mark 15 are laminated on N<+> epitaxial layer 12 on semi-insulating GaAs substrate 11 and successively etched to open a window with length of Lg'. Firstly, N<+> layer is selectively etched to open another window with length of Lg''. The mask 15 is removed to form N type active layer 16 epitaxially in the hole by means of pyrolysis CVD process of organic metal. Secondly, P<+> layer 17 is formed by means of molecular beam epitaxial process. GaAs or Al GaAs or double layer of them may be selected as necessary. In this case, the molecular beams are projected in the two directions of + or -theta to from the film 14 making its hole length Lgo shorter than Lg i.e. Lg>Lgo. An ohmic gate electrode 18 with Lgm Lgo is formed removing the films 13, 14 further forming the other ohmic source, drain electrodes 19, 20. Through this constitution, a device with short gate length may be manufactured easily and evenly.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention L% n-type active layer, p layer and dart'
The present invention relates to a method for manufacturing a high-performance conductor-in-a-compound field-effect transistor of the Brehner type having a homo-metite heterojunction, which is constructed by automatically κ-consolidating the respective relative positions of the k-gold, kI, and I4 fields.

Compared to those using silicon substrates, Kamekai effect transistors using compound semiconductors such as GaAs or TiInP as substrates exhibit very good performance in the area of ultra-high frequency and ultra-high speed damage processing. My wife is well known as a connoisseur.

For compound semiconductor tortoise-effect transistors, a nine-Schottky type is generally used, using a Schottky type for the dart junction, but a homop+1n type or a hetero p+n type is used for an n-type active noodle. p+ has a dart structure of
It is characterized by a large potential difference and a large permissible input signal level.

However, it is much more difficult to construct the p+n junction type than the Schottky junction type, and there are very few prototypes published in the past.
No example of a structure in which an epitaxial a&n'' layer for O is provided has yet been reported.

Also, ^ performance? j! Integration: Integration requires many difficult steps in the device configuration, such as manufacturing fine structure p-n & composite darts, making the device structure lunar, etc., and requires completely new ideas. It is necessary to fly Myanmar based on .

Figure 1 shows the structure of a conventional p-E1m compound conductor field effect transistor.
pn type GaAg is grown on the aAa substrate 1 by epitaxial growth.
The active layer 2 and the p-type semiconductor NI3 are layered, and the p+-type semiconductor dot is selectively etched using a resist mask covering the dart junction area to form a mesa-shaped p''-nr-) junction.
a dart electrode 4 in ohmic contact with the p-type semiconductor layer;
A source t&5 and a drain tom &6 of ohmic contact are provided for n-type activation.

This conventional structure has the following important drawbacks.

That is, in the W,1- structure, the source and drain electrodes are in a-contact ohmic contact on the n-type active layer, and such a structure has a low resistance ohm t! E-contact cannot be obtained, which is a major obstacle to improving the island performance of the device.

For Schottky junction type device #&, semi-insulating GJLAI
Starting from a substrate laminated with n-type active layer, nNII, and t on the substrate, the n layer of the source and drain region is selectively etched by digging and etching the n layer of the dirt region. Is it possible to grow nNa in a p''-nk association type device structure by epitaxial growth?
tin+ in the source and drain regions for the n-type active layer
However, in the dirt region, completely different semiconductor layers, namely the p+ body layer, must be in contact with each other, so that the usual formation of 8 from an epitaxial substrate is essentially impossible.

In the conventional structure shown in FIG. 1, at least a p-type layer is formed between the gate electrode and the source and drain electrodes by selectively etching the p-semiconductor layer to form a mesa-like p+n group. This essentially creates a step difference greater than the thickness of the semiconductor field, which not only becomes an obstacle to the fine structuring of the formation of each pole, but also constitutes a serious drawback of the platform having a multi-sensor configuration.

Furthermore, with the conventional structure that makes it easy to set nNII, n1p+
Since the relative positional relationship between the source and the drain with respect to the n-gate junction is involved in the additional resistance between the source and the gate and between the dart and the drain, it is necessary to Mask alignment technology is required, which imposes restrictions on the short gate length and fine structure of devices, and is an impediment to uniform product performance.

This invention was made to eliminate the above-mentioned conventional drawbacks, so it is possible to improve the precision of the element 5aoijb, and also to improve f#I3 nesting and high 8: performance leveling in the process. How to manufacture a compound bullion-like field-effect vermilion transistor that can achieve ultra-high performance lunarized wood structure and easily integrate elements.
The purpose is to provide

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the method for manufacturing a compound semicircular tortoise-effect transistor of the present invention will be described below with reference to the drawings. Second
Figures (&) to Figure 2 <6) are 11! of one example! !
Parent #3 figure appears. First, 1J of 1J in Figure 2-) is applied to the n+ type conductivity on the surface of the semi-insulating GaAs substrate 11.
A layer 12t is formed by epitaxial growth, and furthermore, two layers of the two types 13 and 141, which can be etched selectively to each other, are provided on the surface thereof, and a resist mask 15 is provided on the resist mask 15 for selective etching. By #! A gate voltage thr with an opening length Lgo is applied to the insulating film 14 of No. 2.
I@forms the mouth.

IP, the second absolute & 13.14 and the 5ilN
4 and StO, in one embodiment where the membrane is overused, the etching solution used is one having a very slow etching rate as 5i (h) to 81 s N4, such as filtrate solution.

next,#! 2, using the mask 13 as a mask, an opening in the f-) region with an opening length Lg' is opened in the first insulating film 13.

In this case, 5is is used for 8103 like hot phosphoric acid.
It has a much slower etching rate than N4 and has very little etching effect on GaAs.
, use.

#p, 2 melting (b) In the o process, use the same first aperture kk13 as a mask that was opened in the previous process, even if using d sulfuric acid-based etching solution! 70aAa Selective etching of the n+ layer is performed to remove the n islands in the f-) area to form an f- of length Lg''.
) Provide an area excavation section.

Next, the resist mask 15 is removed, and an n-type semiconductor active layer 16 is formed in the dug portion of the dirt region using the first and second insulating groups 13 and 14 as masks by selective embedment epitaxial growth.

As a selective epitaxial growth method in this case, it is of course possible to apply the vapor phase A-layer method using the halodan method using electricity. &f-) Good epitaxial growth can be achieved even around the trenched area, and semi-insulating G
The impurity 111 in the boundary direction between the aAs substrate and the epitaxial active layer [organic gold^ pyrolytic CVD method] is used for reasons such as less droop in the distribution and better controllability of the active layer growth film thickness. is optimal.

In the step shown in FIG. 2(c), a dart junction p-type semiconductor layer 17 is formed by molecular beam epitaxial method using the second insulating group 14 as a mask. n-type GaAa '@- dart junction p + half 4 of tortoise field effect transistor with active 1
As a body class, in the case of homop+-nm combination, the p form Ga
If the As floor is a heterop+n combination, p
type AtGaAs or p type AtGaAs+- and p
The 21st floor of the form QaAa floor applies.

In the formation of a p-semi-quaternary layer by the molecular beam epitaxial method, as shown in Fig. 2(c), a p-quadram layer is formed from two directions tilted by an angle θ in the positive and negative directions with respect to the non-orthogonal axis of the substrate surface. By using the film 14 as a mask, the second
Lg > Lgo for the gap & opening length Lgo of the membrane 14
It is possible to obtain a p-semiconductor layer length Lg of and different properties effectively #
This is what I did.

#! In the step shown in FIG. 2 Gi), a dirt electrode 18 is formed by using the second insulating film 14 as a mask to form a vacuum layer of gold which exhibits ohmic vibration with respect to the p+ semiconductor layer.

In this case, by making the # layer direction of the metal approximately bloodless toward the substrate, the p1 gate voltage tj length Lgm line Lgm:Lgo
<Lg.

Figure #42 (In the process, after removing the second and first insulating groups, the source of ohmic vibration for tLnjl is determined by the usual Mengen-drawing-vacuum-writing-Litoff method. Electrode 19
And the drain electric fik20t- is of the duck provided.

As is clear from the above reading, in the present invention, the surface of the semi-insulating GaAs substrate 11 has an n+ type conductivity.
#, l and a second constant film 13 of two f11Ir14 which can be etched selectively to each other on this surface.
．． 14 is provided, a dart electrode narrow opening with an opening length Lgo is formed in the insulation ai14 of wI2 on the outermost surface, and the first insulation film 13 is selectively etched using the second absolutely exposed film 14 as a mask to form a mouth length Lg'. f-) region opening t'' is provided, and further Ig
Using the insulating film 13 of 1 as a mask, selective etching of GaAsn 1i is performed, excluding the
"The dirt area excavation part is formed, and the Lg that was formed in this process.

＜Lg'＜Lg'' in the digging part of the dirt area
A type of GaAs active layer 116 is selectively buried epitaxially formed, and then the second insulating film is used as a mask to form a molecule-1 epitaxial method from two directions that form a fixed and negative angle with respect to the non-perpendicular axis of the substrate surface. Alternatively, form 91 layers 17 of Hete Hop”-n combination type dirt, and further #
! 2. Using the membrane 14 as a mask, use the vacuum method
The gate electrode 18t has a gate electrode length Lgm such that m=Lgo<Lg<Lg'<Lg".

Therefore, in this invention, first, the conventional p+
In an n-junction compound semiconductor field effect transistor, it is possible to achieve epitaxial nil in the source and drain regions, which was not possible with a multilayer epitaxial structure on an amorphous substrate.
In this invention, the selective embedding epitaxial growth method is applied to solve the setting, and the main AI performance can be improved.

Moreover, in the manufacturing method of this invention, tl! Insulating film 1 of 1 in order from the gate 11 of the insulating group 14 of 12
3. Each mask effect continues to leak into the n+ layer, and each layer is etched to form a 1m dirt area, and these insulating film masks are used for the n-type active layer and p+ semi-semiconductor color-selective epitaxial growth. The relative position of the source and drain/p''-n-layer-) junctions to the n-layer and active layer boundaries, and the p+ The relative position #IIL relationship with the semi-semiconductor color f-) electrode both has a large % value that is automatically set.

This eliminates the difficulty of mask alignment in manufacturing a gL#1 structured device with a short gate length, and contributes to process simplification and uniform product performance.

Next, as an attractive effect of providing the first 13, it plays the role of making it possible to configure a desired cage with a uniform ratio of Lg and Lg''.

That is, in the case where the first insulating film 13 is not provided and the n-layer is directly etched using a portion of the twentieth insulating film 14 as a mask, the lateral etching is determined in relation to the etching cover in the depth direction. Whereas the shape of the trenched portion, that is, the ratio between Lgo and Lg'' is limited depending on the amount, by providing the first and second insulating films 13 and 14 of the present invention, the first insulating film 13 Bite length Lg/Mineral Lgo
(Lg' can be set relatively freely, and this Lg
``Lg'' has the great effect of making it possible to set the amount of inset etching to the desired koji of F9T, and to make it possible to create a large amount of heat.

In addition, regarding the setting of the gate electrode for the p + half-body scale, we applied the molecular beam epitaxial method with antennae attached and also used the insulating film in 2 as a mask, so we decided to use a short dart Nagiko. Even if Lgm < Lg
(DlnI can be precisely set and the relative position wIL relationship can be set automatically, so that problems such as combination accidents of p+n type gate junctions due to dart electrodes do not occur.

Furthermore, by designing the depth of implantation in the gate region to be approximately the same as the sum of the predetermined thicknesses of the n-type active layer and the p-half body layer, the source and drain electrodes on the s n''N It is possible to realize a Brehner-type device structure in which the dart electrodes and the dirt electrodes are at the same angle as t, which is extremely effective not only for individual devices but especially for integrated device configurations.

The effect of the above-mentioned method of making rice according to the present invention is shown in terms of constant current using an embodiment of the maximum setting needle. Each 0.1 μ earthquake, Lg
For the case of o=0.7μ vote, Lg'==1.3
fig, r −) area digging depth = 0.25 nsi, L
g" = 1.8 μs, n-type active layer thickness g = Q, l, u layer, p++ conductor layer thickness = o, i sμ, molecular line inclination 0
= ±30°, Lg”1.4mm, Lgm = 0.7μ
It becomes possible to manufacture a high-performance microstructured tree with a long gate length and an extremely reduced direct resistance between the source and the drain.

As described above, according to the method for manufacturing a compound semiconductor field effect transistor of the present invention, after forming an n-type conductive layer, a layer, and a second insulating film on a semi-insulating compound semiconductor substrate, these layers are Selectively etching is performed to form an f-) area excavation part, and an n-type compound semiconductor active layer is formed in this gate area excavation part, and the same 8 [or different type A p+ positive layer of a compound semiconductor is formed to form a p layer constituting a p+-n vibrational dart, and a gate electrode is formed on this p layer, so it is difficult to obtain good ohmic contact. Even in a structure in which an n+ layer is set and the distance between the source and drain is minimized, the relative positional relationship between the p+ n type (r-) junction and the f-to electrode is automatically set, resulting in a Kameko configuration. Achieved Ib accuracy and improved process efficiency! Excellent effects such as a very high performance planar element structure can be realized with uniform performance due to ice formation, and integrated elements can be easily formed.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing the structure of a conventional p+n junction type compound semiconductor field effect transistor, and Figures 2 (aJ to 2e) illustrate the manufacture of the compound semiconductor field effect transistor of the present invention, respectively. An embodiment of the method &! Appearance 9i
It is a diagram. 11... Semi-insulating GaAs substrate, 12-n @, 1
3...l! 1 Zononi Membrane, 14...2nd Zononi Hen, 1
5...Resost mask, 16...n cedar oxen body active a pigeon, 17... dart junction p semiconductor layer, 18...r-
)-pole, 19... drain tkszo... source electrode. Patent Applicant Oki-Kikou Co., Ltd. Procedural Amendment Letter Arrived September-3, 1980 by the Commissioner of the Patent Office # Kazuo 1, Indication of the Case 1939, Request for Application No. 552 @ 9 2, Issued #io Name Electric field effect on conductors in buildings 10 Gisei construction method 3, relationship with the case of the person making the amendment Patent Applicant (0!9) Oki Electric Works Co., Ltd. 4, Agent 5, Date of amendment order Month, Showa to spend a day (mostly).

Claims (1)

[Claims] Sexual compounding for abortion - Kn-type conductive field on a conductive substrate and two types of first and second types that can selectively etch each other
Insulating film of 1 is formed, a narrow hole T- is provided for installing an electrode on the second insulating film at the outermost surface, and the insulating film of Figure 1 is traced using the second insulating film as a mask. Open etching and selective writing etching of the n + -type conductive layer using the first insulating film as a mask are performed to provide a dirt region entry portion, and an n-type compound semiconductor active NiI is formed in this dirt region fence portion. , using the second insulating film as a mask from two directions, which serve as positive and negative antennae with respect to the vertical axis of the semi-insulating compound semiconductor substrate iii, using a compound of the same polarity as the n-type bovine body active pigeon or the US strain. A p-layer of semiconductor is formed to form a p-layer constituting a p+-n trapezoid (r-), and a p-layer is formed inside the semi-insulating compound semiconductor substrate. &! Good side same direction second insulation 1111 - P as mask! A method for manufacturing a compound semiconductor field effect transistor, which comprises forming a gate electrode gold #1NjI as an ohmic contact on I11.