JPS6256041A - Clock matching circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by selecting any one clock out of clocks outputted from a frequency division circuit depending on the software control and outputting it as a data latch clock to a data processing circuit. CONSTITUTION:The frequency division circuit 10 makes reception clock from an oscillator 7 4 layers in clock. The selector 4 selects any one of the clocks subject to 4-layer based on the software control and gives it to a FF 3 and a data processing circuit 5 as a data latch clock. The FF 3 uses the data latch clock to latch the data transferred from he data transmitter 1. The data processing circuit 5 applies the bit synchronization and data processing by using the data from the FF 3 and the data latch clock from the selector 4. Thus, a simple clock matching circuit is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock matching circuit for a data receiving system in a data transfer device.

[Conventional technology]

Conventionally, this type of clock matching circuit has been equipped with a multi-stage flip-flop circuit or a memory circuit that can perform writing and reading asynchronously, taking into account the phase difference between the clocks of the opposing device and its own device.

FIG. 4 is a block diagram of a conventional example of a clock matching circuit used in a data transfer device that performs data transmission using a bit-synchronized transmission procedure.

Data transmitted by the data transfer device 1 and a clock synchronized with this data are taken into the self-equipped Go via the receiver 2. Next, since the duty cycle of the clock is usually different from that transmitted by the data transfer device M1 depending on the length of the transmission path and the transmitting/receiving element, the duty cycle correction circuit 3 ensures that the received data is written to the next stage. The duty cycle of the clock is corrected so that 1 can be stored in the read asynchronous memory 4.

The clock emitted from the oscillator 7 or counted down by the frequency dividing circuit has the same frequency as the received clock, and the received data stored in the memo () 4 is read out. The data is passed to the data processing circuit 5.

When the check circuit 6 detects that the reception clock is cut off, it reports this to the CPU 8. The CPU 8 can control the memory 4 or the data processing circuit 5 to stop processing the received data depending on the contents of the check circuit 6.

FIG. 5 is a block diagram of a clock matching circuit used in a data transfer device of the word synchronous type, that is, a data transfer device that assigns meaning to several bits and several bytes.

The difference from the clock matching circuit shown in FIG. 4 is that a synchronization pulse indicating the beginning of information is added, and the timing circuit 10 necessary for generating the timing required to store 1 into the memory 4 for each unit of information is similar to that of the clock matching circuit shown in FIG. A timing circuit 11 necessary for reading unit information from the memory 4 is added to the memory 4.

[Problems to be Solved by the Invention] The conventional clock matching circuit described above performs matching control using only hardware logic. The disadvantage is that the peripheral hardware of the memory circuit is large, and that very complicated hardware is required when matching is achieved using multi-stage flip-flops without using memory.

c) Means for Solving Problems) The clock matching circuit of the present invention includes a frequency dividing circuit that divides a data reception clock and outputs a plurality of clocks having mutually different phases, and a flip-flop that latches received data. , has means for selecting one of the clocks output from the frequency dividing circuit under software control and outputting it as a data latch clock to a flip-flop and a data processing circuit that processes latch data of the flip-flop.

In this way, by dividing the data reception clock to obtain clocks with mutually different phases, and selecting one of these clocks under software control,
high number of flip-flops)? Only two pieces are required, and the circuit configuration is simpler than when using memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram of a bit-synchronized data transfer device having an embodiment of the clock matching circuit of the present invention.

The frequency dividing circuit 10 divides the data reception clock from the oscillator 7 into four layers (divides the frequency to obtain four clocks P having mutually different phases). The selector 4 selects one of these four layered clocks under software control using crt+s, and uses it as the data latch clock.
It is supplied to the flip-flop 3 and the data processing circuit 5. The foot flop 3 latches the data transferred from the data transfer device 1 using the data latch clock. The data processing circuit 5 performs bit synchronization and data processing using the data from the flip-flop 3 and the data latch clock from the selector 4. It is equipped with a circuit that determines whether or not it has occurred. cpu
s can read this information, and by reading this information, it can be determined whether the clock that has been supplied to the data latch flip-flop 3 is appropriate, and by appropriately switching the latch clock via the selector 4, It is possible to extract a clock that operates stably.

FIG. 2 is a block diagram of an embodiment in which the present invention is applied to a word synchronous type data transfer device. This is similar to Figure 1, but the clock transmitted from the opposing data transfer device is not used.The difference with Figure 1 is that the opposing data transfer device sends a synchronization pulse indicating the beginning of the data. The clock layered into four layers by the frequency divider circuit 10 is latched by a synchronous pulse using a flip-flop), the result is read by the CPU 8, and the software determines which of the four layered clocks should be selected and controls the selector 4. It is something to do.

FIG. 3 is a time chart of the embodiment shown in FIG. Oscillator 7 oscillates and frequency divider circuit 1 is based on 1 clock.
0 four-layer clock 5irS7, S3r
S4 is output. The output is input to flip-flop 11 and latched by the synchronization pulse. When the CP 118 reads the output of the flip-flop 11, it reads the data "1000", converts this, and uses the selector 4 to determine which layer's clock is to be used for the received data. In this case, clock S3 is selected and input to flip-flop 3 and data processing circuit 5.

〔Effect of the invention〕

As explained above, the present invention divides the data reception clock to obtain clocks having a number of different phases from each other, and selects any one of these clocks under software control. A simple lock matching circuit can be constructed, lock matching can be performed at low cost, and high quality, and data transfer delay can be kept within one reception delay.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data communication device (an example of application to a bit-synchronized data transfer circuit) including an embodiment of the clock matching circuit of the present invention, and FIG. 2 shows an embodiment of the clock matching circuit of the present invention. 3 is a time chart showing the operation of FIG. 2, and FIGS. 4 and 5 include a conventional clock matching circuit. FIG. 4 shows an example of a data transfer device, and FIG. 4 shows a bit synchronous type, and FIG. 5 shows a word synchronous type. DESCRIPTION OF SYMBOLS 1... Data transfer device, 2... Receiver-5 3, 11... Flip-flop, 4... Selector, 5... Data processing circuit, 6... Check circuit, 7... Oscillator , 8... CPU, 9... Memory, 10... Frequency dividing circuit.

Claims (1)

[Claims] A clock matching circuit for inputting received data transferred from an opposing data transfer device at the same clock rate into a data processing circuit within its own data transfer device, which separates the clock for data reception. A frequency divider circuit that outputs multiple clocks with different phases, a flip-flop that latches received data, and one of the clocks output from the frequency divider circuit is selected by software control, and the flip-flop and A clock matching circuit having means for outputting a data latch clock to a data latch circuit.