JPH02281837A - High speed frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To use the protection network of an inexpensive circuit constitution by bringing DATA and CLOCK which are inputted to frequency division in a prescribed frequency division ratio and outputting them, respectively. CONSTITUTION:A clock (CLOCK) is brought to frequency division in a prescribed frequency division ratio in a frequency dividing circuit 15 and brought to all phase output, and by a pulse detecting circuit 20 and a selecting circuit 25, one of the outputs brought to all phase output is outputted as a frequency- divided output. Also, input data (DATA) synchronizing with the CLOCK is outputted as extended pulse width by a D-type flip-flop 10, based on the CLOCK which is brought to frequency division and all phase output. In such a manner, the protection network of an inexpensive circuit constitution for operating by a low frequency, comparing with the transmission rate of the DATA and the CLOCK which are inputted can be used, and the whole device can be obtained at the low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed frame synchronization circuit that synchronizes high-speed transmission signals.

[Prior Art 1] For example, the transmission speed of transmission signals used for data transmission has been increasing. Along with this, efforts are being made to speed up the processing of frame synchronization circuits that process frame signals included in transmission signals.

Here, the frame synchronization circuit roughly consists of a frame matching circuit that detects a frame signal, and a protection circuit that determines whether the frame signal is synchronized by forward protection and backward protection, and a transmission signal is input to the frame matching circuit. Then, a frame signal is detected according to a predetermined pattern, and a subsequent protection circuit performs processing to determine whether synchronization conditions are satisfied. In other words, if several consecutive normal frame signals are input, each signal is determined to be synchronized (forward protection), and if several consecutive abnormal frame signals are input, each signal is determined to be synchronized (forward protection). It is determined that the signals are not synchronized (backward protection).

[Problem to be solved by the invention] However, the transmission signal currently used is 6221
bit/s, 1, 8Gbit/s, 2, 4Gb
IT/s, so special circuit components for high-speed processing are required to configure the protection circuit, and the circuit configuration becomes complicated. , 2, there is no protection circuit for 46 bit/s.

Therefore, the protection circuit is constructed with components that can operate at low frequencies.
One possible method is to provide a pulse width stretching circuit that outputs a lower frequency by changing the pulse width of input data, and to operate the protection circuit at this lower frequency.

This pulse width stretching circuit consists of a mono-multi-by-break, delay and gate OR circuit with a certain time constant,
Further, by using a shift register or the like connected in series, a pulse having a width larger than the input pulse width can be obtained. This makes it possible to use current protection circuits that can operate at low frequencies.

However, with the above configuration, although the frequency of the input signal itself can be lowered, a clock corresponding to the input signal necessary for the operation of the protection circuit cannot be obtained. Further, since the above configuration is fixed only to a certain predetermined frequency, it cannot support transmission signals of various transmission speeds as described above.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a high-speed frame synchronization circuit that can use general-purpose parts and a protection circuit with an inexpensive circuit configuration.

[Means for Solving the Problems] In order to achieve the above object, the high-speed frame synchronization circuit of the present invention includes a frequency dividing circuit (15) that divides the input clock (CLOCKI) at a predetermined frequency division ratio and outputs all phases. and data fDATA input based on the output of the frequency dividing circuit.
) and a pulse detection circuit (20) that outputs according to the detection result; and a selection that selects and outputs one of the all-phase outputs of the frequency dividing circuit that is input depending on the output state of the pulse detection circuit. A circuit (25), the output of the selection circuit is connected to the clock (C) terminal, and the data is connected to the data (D) terminal, so that the data +5TR is output according to the frequency-divided clock.
The present invention is characterized by comprising: a D-type flip-flop (10) that outputs ECHED DAT^); and a terminal (30) to which a converted clock signal, which is the output of the selection circuit, is supplied.

[Function] The clock is divided by a predetermined frequency division ratio in the frequency dividing circuit and outputted in all phases, and the pulse detection circuit and the selection circuit output one of these outputted phases as a divided output. . In addition, input data synchronized with the clock is
D-FF based on the divided clock and all phase output
The pulse width is output as an expanded pulse width.

[Embodiment 1] As shown in FIG. 2, the high-speed frame synchronization circuit l includes a frame matching circuit 2% pulse width stretching circuit 3, and a protection circuit 4.
The input data DATA (
In the NRZ), after a frame coincidence signal is detected by a frame coincidence circuit 2, a frame coincidence judgment is made by a protection circuit 4.

FIG. 1 is a diagram showing an embodiment of the high-speed frame synchronization circuit of the present invention.

The five pulse width stretch circuits 3 are provided between the frame matching circuits 2 and the protection circuits 4.

Input data DA after being output from frame matching circuit 2
TA is input to a data input (D) terminal of a D-FF (D-type flip-flop) that constitutes the synchronous circuit 5. On the other hand, CLOCK, which is supplied simultaneously with the DATA, is input to the clock (C) terminal.

Furthermore, the output terminal Q of the synchronous circuit 5 is connected to the output terminal D-
Connected to the D terminal of FF I O.

The C terminal of this D-FF lO is connected to the selection circuit 25 which will be described later.
The output terminal (Q) of this D-FFIO is connected to the output terminal Q of the D-FFIO.
Output RECHED DATA.

In addition, 15 is a frequency divider circuit which lowers the CLOCK to a predetermined value (in this embodiment, divides the frequency) and then divides the CLOCK into a predetermined value.
All phases are output from 5a and 15b.

On the other hand, the DATA output from the C terminal of D-FF5 is
Two D-FFs 21 and 2 forming the pulse detection circuit 20
It is input to the D terminal of No.2. The C terminal of the D-FF21 is connected to the output terminal 15a of the frequency dividing circuit 15, and the C terminal of the D-FF22 is connected to the output terminal 15a of the frequency dividing circuit 15.
The terminals are respectively connected to the inverting output terminal 15b of the frequency dividing circuit 15. 1) The output terminal Q of -FF21 is
It is connected to the S terminal of R5-FF23, and the output terminal Q of D-FF22 is connected to the R terminal of R5-FF23. R3
The output terminal Q of the -FF 23 is connected to the S terminal of the selection circuit 25. Further, the output terminal 15a of the frequency dividing circuit 15 is connected to the selection input terminal 25a, and the output terminal 15b is connected to the input terminal 25b. Then, the selection circuit 25 switches all the phase outputs of the frequency dividing circuit 15 to either one depending on the level state of the S terminal, and outputs it from the output terminal 25c to the C terminal of the D-FF I O.

Further, the output of the output terminal 25c is outputted from the terminal 30 as a clock signal for operating the protection circuit 4.

Next, the operation of the above configuration will be explained using the timing chart of FIG. 3(a).

The input DATA having a pulse width Tl is output by the synchronization circuit 5 as a signal S[ synchronized with CLOC input at the same time.

On the other hand, after being frequency-divided by the frequency dividing circuit 15, CLOC receives an output S2 from the output terminal 15a and an output S2 from the output terminal 15b.
is output as an inverted output S3.

Next, the D-FF 21 of the pulse detection circuit 20 holds the signal Sl for one cycle from the rising edge of 82 and outputs the signal S4. In one D-FF 22, when the signal S3 rises, all the signals Sl are in the "L" state, so the signal S5 at the output terminal Q remains in the "L" state.

Therefore, the R3-FF 23 outputs a signal S6 holding a signal in the "H-state" based on the fact that the signal S4 is in the "H" state and the -L" state of the signal S5.

Then, the selection circuit 25 selects the signal S4 based on the signal S6 and supplies the signal S2 to the terminal 30 and the D-FFIO.

D-FF I O holds the signal Sl for one cycle at the rising edge of the signal S7 and outputs 5TRECHED DATA. As a result, the D-FF I O receives the input D
The pulse width T is expanded by dividing the ATA pulse width TI.
2, 5TRECHED DATA will be output. In addition, 5TRECHED by D-FF I O
The output of DATA is configured to start from time t2 based on signal St rising at time 11.

In this way, the input data is supplied to the protection circuit 4 as 5TRECIIED DATA which is expanded twice. At the same time, a signal obtained by frequency-dividing the CLOCK is output from the terminal 30, so that the protection circuit 4 in the latter stage is a circuit I that operates at a frequency within the transmission speed of the input DATA.
A type II structure can be used.

Moreover, FIG. 3(b) shows the frequency dividing circuit 1 in FIG. 3(a).
5 is inverted and output at output terminals 15a and 15b. When the frequency dividing circuit 15 is powered on, the output states of the two output terminals may be inverted. At this time, the signal S2. Although S3 is reversed from the state shown in FIG.
Based on the detected signal S5, R5-FF23 becomes ``L''
Output a signal. As a result, the selection circuit 25 operates as shown in FIG.
Compared to a), the signal 8 on the output terminal 15b side of the frequency dividing circuit 15
Since the third side is selected and outputted to the D-FF 10, the operation is the same as that shown in FIG. 3(a) regardless of the power-on state.

Next, FIG. 4 shows another embodiment of the pulse width stretch circuit 3 portion according to the present invention, and the same components as those in FIG.

In this embodiment, a delay circuit 4o is inserted between the synchronous circuit 5 and the D-FF 10, and the delay circuit 40 is composed of two D-FFs 41 and 42 connected in series, and the signal Sl and the CLOCK is input, signal Sl
The pulse width Tl is delayed by twice and supplied to the D-FFIO as a signal Sl'. As a result, as shown in FIG. 5, it is possible to output 5 TRECHED DATA corresponding to the synchronized signal St (occurrence time tl') of the first input DATA at the same time t2 as in the previous embodiment. As a result, the frequency division operation can be performed starting from the first DATA, which was not detected and dropped in the embodiment shown in FIG.

In all of the embodiments described above, the input DATA is frequency-divided, but the frequency division ratio can be set arbitrarily, and in this case, only the frequency divider circuit 15 is configured to have an arbitrary frequency division ratio. For example, two remaining frequency dividing circuits can be connected in series to perform low frequency division, and with this selection alone, DATA inputs of various transmission speeds can be supported.

In addition, in this case, the relationship between DATA and the frequency division ratio is
Is it necessary to input the input to the NXM bit?

However, N: Number of frequency dividing circuits M: An integer of 1 or more [Effects of the Invention] As explained above, according to the high-speed frame synchronization circuit of the present invention, input DATA and CLOCK are divided by a predetermined frequency division ratio. There are effects that can be obtained from each.

Therefore, it is possible to use a protection circuit with an inexpensive circuit configuration that operates at a lower frequency than the transmission speed of input DATA and CLOCK, which has the effect of reducing the cost of the entire device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the main parts of the high-speed frame synchronization circuit of the present invention, and FIG. 2 is a block diagram of the same high-speed frame synchronization circuit.
3(a) and 3(b) are timing charts showing the operation of the same circuit, FIG. 4 is a circuit diagram showing another embodiment of the present invention, and FIG. 5 is a timing chart of the same. ■...High-speed frame synchronization circuit, 2... Frame matching circuit, 3... Pulse width stretch circuit, 4... Protection circuit, 10...-D-FF, 15-- Frequency division circuit, 20-
- Pulse detection circuit, 25... selection circuit, 30... terminal. Patent applicant Norihiro Nishimura, Anritsu Co., Ltd. agent/patent attorney, Hikaru L continuation amendment (voluntary) May 31, 1999

Claims (1)

[Claims] A frequency divider circuit (15) that divides an input clock (CLOCK) at a predetermined frequency division ratio and outputs all phases, and data (DATA) that is input based on the output of the frequency divider circuit. detect,
Pulse detection circuit (20) that outputs according to the detection result
and a selection circuit (25) that selects and outputs one of all phase outputs of the frequency dividing circuit inputted according to the output state of the pulse detection circuit, and the output of the selection circuit is connected to a clock (C) terminal. and a D-type flop-flop (10) that outputs the frequency-divided data (STRECHED DATA) according to the frequency-divided clock by connecting the data to a data (D) terminal; A high-speed frame synchronization circuit comprising: a terminal (30) to which a converted clock signal which is an output of a selection circuit is supplied;