JPS58184886A - Clock reproduction system - Google Patents

Abstract

PURPOSE:To attain a stable and sure clock reproducing operation, by comparing the leading time point of plural clock signals with the generated time point of a pulse phase-synchronized with a bit synchronizing signal, and taking a clock signal rising at first as a decoding clock signal. CONSTITUTION:A clock signal 20 in 5.78MHz is applied to a tapped delay line 16, delayed clock signals 21-1,21-2... are picked up in parallel and applied to phase discriminating circuits 17-1,17-2.... The circuits 17-1,17-2... bring output selection pulses 22-1,22-2... to ''1'' in response to the impressing of a timing signal 26 accurately phase-synchronized with a clock synchronizing signal. While a reset pulse from an NAND gate 18 is ''0'' and the output selection pulses 22-1, 22-2... of the circuits 17-1,17-2... are ''1'', the clock pulse of the signals 21-1, 21-2... rises and goes to ''1'' at a phase discriminating circuit only, the output selection pulse level is brought to ''0'' and the input delay clock signal is taken as a reproducing clock signal.

Description

[Detailed description of the invention]

What is the present invention? In a teletext receiver, etc. that receives broadcasts that include a character code signal having a code signal of the III Goyogo, the Odaiba in the Ukkoku-go is detected based on the bit synchronization signal included in the Ukkoku-go. Concerning a clock regeneration method for regenerating a decoding clock signal for a signal (2) In particular, a clock signal that is precisely phase synchronized with the sign polarization in a received signal can be regenerated with extremely high precision using a simple configuration. First, a preferred example of the application of the clock regeneration method of the present invention and a brief explanation of the signal format and the mode of reception and demodulation in the above-mentioned teletext broadcasting. In the teletext signal and U~, for example, in one predetermined horizontal scanning period in the vertical blanking period of the television video signal, the first
Literature information signals configured as shown in the figure are multiplexed in packet format. The illustrated data bucket consists of a header HD and information data [DT, and the header WHD is
Arrangement 1. at the front of the data packet. A group of control code signals for performing digital synchronization, backt identification, etc., including a clock run-in OR and a data packet D consisting of a bit synchronization 1st code sequence for reproducing 1ft of clock signal.
Framing code FC for frame synchronization of T
, a service identification interrupt code indicating the service identification and interrupt of a data packet, and a data identification code DI (Dll, DI, ) for identifying the m class of DT (data bucket). The information data portion DT is the remaining portion following the above-mentioned header portion HD of the data packet, and is the remaining portion of the data packet, and is the remaining portion of the image 1! It is for transmitting information data such as l+i information, color information, and information regarding the page of th My Gland Tachibana. Among those information data, -image f
4th degree information is 2 fli digital information 4I obtained by scanning patterns such as letters and figures! The color information is an encoded digital signal of characters and figures, and color information regarding the pattern, control information for reproduction table, etc. are also generally encoded digital signals. In order to receive the character information signal having the above-mentioned configuration and convert the required information data into *D4, a predetermined repetition [[ ~Frequency paste・1:・・・・ Lock 1!!11 is regenerated, and each frame of the data packet is synchronized using the regenerated clock signal and the framing code FO in the receiving code, and the 11th small * Therefore, in order to reproduce the received character information signal without error, - the phase of the above-mentioned reproduced clock signal must be accurately matched with the phase of the digital signal in the received character information signal. The most essential requirement is to match the data packet.The configuration of a conventional clock recovery circuit that satisfies this essential requirement is shown in FIG. 2.In the conventional configuration shown in the figure, Chrono run-in gate circuit 11C reception for extracting clock run-in OR in

[~ta character information f! Extract clock run-in OR by supplying I-Q and applying No. 6 gold to the gate formed according to the input of the character information signal data packet 17;
This clock run-in signal, which is a bit synchronization signal, is supplied to the ORi ringing circuit 2. The ringing circuit 2 is
A narrow band pass P-wave device using a crystal oscillator 1 with an appropriate frequency performs all of the following functions: 1. Clock run in O
R generates ringing having a repetition frequency of -the same repetition frequency as the clock frequency. 1 and supplies the output signal to an 8-multiplying circuit 8.
Then, the repetition frequency is doubled by ir, so that Jle times the number of reproduced clock signals can be extracted. (2 or 1) Therefore, a conventional clock regeneration circuit using such a ringing circuit regenerates a clock signal with a simple circuit configuration (2) However, the clock phase is disturbed when ringing occurs in the ringing circuit 2. Therefore, it has the drawback that it is difficult to obtain a Nii-ri lock signal that accurately has an appropriate phase with respect to the digital signal in the received text information signal. In a conventional clock regeneration circuit having the configuration shown in FIG. 8, which is capable of regenerating a clock signal having an appropriate phase with respect to an input digital signal with accuracy, Extremely high oscillation wave number, for example, oscillation frequency of about 2
8 Supply to the town counter 5 of MH2 and synchronize the phase with the clock run-in OR in the received [character information signal] 5.7a MH2's required repetition frequency and clock run-in Take out the recovered clock signal with (7). [7 or [
, Therefore, with the conventional circuit having such a configuration, a phase synchronization accuracy corresponding to a time difference of about 85n8 at most is obtained with respect to the phase of the reproduced clock signal, and the precision of the phase synchronization is only 1.
In order to achieve this, it was necessary to further increase the oscillation frequency of the original oscillator 4. However, if the excavation frequency of the original oscillator 4 is made much higher than, for example, the above-mentioned 28 MHz, the oscillation output signal at the high frequency will be transmitted to other circuits of the character information signal receiver through the stray capacitance of the circuit. There is a drawback that other undesirable interference noises may be generated by coupling 1/1 to the IL connection or by interfering with other receivers. Eliminate the above-mentioned drawbacks of the conventional configuration shown in Figure 3 (2)
Without making the excavation frequency of the nuclear power plant #i reactor 4 as high as mentioned above, the phase synchronization frequency of the regenerated clock signal can be changed to the reform II [7
The configuration of the conventional clock regeneration circuit is as follows.
As shown in the figure. In the conventional configuration shown in the figure, the required frequency, for example, 5.713 M extracted by a crystal generator or the like, is used.
Supplying the recovered clock decoded lO of H2 to a tapped delay line 6, for example, a plurality of 5.78 MHz clock signals 1t sequentially having phase differences corresponding to a time difference of 1018 are sequentially arranged in parallel, The clock signal group is supplied in parallel to the latch circuit 7 and the data selector 9. Latch pulse 1
2 is applied, and the launch information of the input delay clock signal group at the time point 1=mLt is latched to the phase of the latch pulse, and the launch amplitude information group]8 is extracted, and the latch amplitude information group 1δ is used as an address to be stored in a read-only memory. (ROM
) 8. The read-only memory 8 stores 5,73 MHz clock signal signals which are sequentially taken out in parallel from the delay line 6 and which shoulder a phase difference of K 10 bs.Me information of each delayed clock signal group at every latch timing is stored as an address. j! Information on which delayed clock signal of the delayed clock signal group is selected is stored in advance, and therefore the above-mentioned "address signal" and (
When accessed using the latch amplitude information group 18 supplied in 7, the phase is synchronized with the phase of the latch pulse 12 that formed the latch amplitude information group 18 with a phase fllJj within 10 n8 of the phase difference between the delayed clock signals. Selection information signal 14' that can select delay clock (1!M)
ft can be taken out. Therefore, the selection information signal 14 is applied to the ligator selector 9 to appropriately select one from the group of delayed clock signals supplied in parallel from the delay line 6.
．． So, the phase i within 10n8! It is possible to extract a 5.78 MHz regenerated clock signal with full precision. 1. In the conventional configuration shown in Figure 4, ) 0. L'7+/a5. In order to be able to select the 5,73 MH2 delayed clock signal that is precisely phase synchronized with CC, the variable length of the latch timing, that is, the one period separation of the reproduced clock signal is 174nEi.
In order to achieve this, it is necessary to form approximately 17 sets of delayed clock signals (for example, to double the phase-to-phase delay of the regenerated clock signal). is the phase of the delayed clock signal group; +k
511 seconds, and approximately 85 sets of delay clock signals are required. As a result, the number of address lines increases, and it becomes necessary to use a read-only memory with an extremely large amount of memory. Memorizing this information for each 15-character transmitter/receiver increases the price of the receiver, which poses a problem that hinders the general spread of teletext broadcasting. In a clock regeneration circuit, F, the phase synchronization precision 1 is increased by K, which is extremely high precision of 5 ns, and a tapped delay line with a stable plexus is indispensable.
It is not easy to manufacture tapped delay lines with low R and stable cylinder changes at low cost. Therefore, a high-precision tapped delay line such as a BNS usually has variations in its slow sail output, and when using a delay line that cannot obtain an output with such variations [2], the clock signal at the bottom of Fig. Even when a regeneration circuit is configured, in order to obtain a regenerated clock signal that is correctly phase-synchronized with the input digital signal, the latch amplitude information group]8
For all possible cases that may arise, i.e. 2
This is an essential problem in that not only is an extremely large capacity memory of ×6 bits required, but depending on the contents of the latch amplitude information group 13, it may not be possible to specify the delayed clock signal to be extracted. this. The object of the present invention is the above-mentioned 1. This eliminates all of the drawbacks of the prior art, such as highly accurate phase synchronization of the digital signal in the received next character information signal. No. t-m
The object of the present invention is to provide a clock recovery method that can be recovered by a simple circuit configuration. That is, in the clock regeneration method of the present invention, when regenerating the lock +-i for the subsequent code for the hjJ distribution code signal code 1 based on the bit synchronization signal trap included in the received signal, Repetition of the same code as the bit synchronization code (7) At the rising edge of a plurality of clock signals each having a different phase and having a wave number of 7, and at the time of generation of a pulse phase-synchronized with the bit synchronization signal The clock signal that rises first among the plurality of clock signals according to the generation of the pulse is set as the lock IK code for writing and decoding. Hereinafter, a detailed explanation of the present invention will be given with reference to FIG. In the configuration, tagged delay line 1
6 is the tapped delay in the conventional clock recovery circuit described above with reference to FIG. In the same manner as I6, for example, by multiplying the crystal-originated, quasi-horizontal -, :', :1 sub-signal by 864, or by supplying 20 color clock signals, for example, as shown in FIG. To,
Phase difference! With i nB, the 11th delay [7^85 sets of delayed clock signals 21-1 to 21-86'fr are taken out in parallel. The 85 sets of delayed clock signals 2]-1 to 21-85 are output to the phase determination block 17.
7-86 in parallel. I or 1. Therefore, each phase determination circuit 17-1 to 1 fu 85 is as follows.
In both cases, as will be described later, the input digital signal, such as the digital signal in the received character information signal, is the same as the input digital signal.
In response to the application of the set pulse 26 having a timing that is phase synchronized with K phase, that is, a timing that is precisely phase synchronized with the clock run-in OR which is the clock synchronization signal described above, it is determined that the phase has started and the output selection pulse is output. 22-
1 to 22-85 are all set to a high logic level "]", and when the reset pulse 26 from the Nantes gate 1B is at a low logic level "0", all the phase determination circuits 17
-1-17-35 output selection pulses 22-1 to 22-8
5 is set at high logic level "1" ~), the input delay clock signal 2]-]~21-δ5 clock pulse rises and reaches the high logic level "'1" only in the relevant phase determination circuit. At the same time, when the output selection pulse is set to If': m processing signal ``θ'', the manual input lock signal of the phase determination circuit is expressed as a regenerated clock signal. l, therefore, each phase determination circuit 17-1 to l 7-83
vC1 Condolence Figure 6 e As shown in this figure, the delay of Cronquis G 21-1, 21-2, ・, 2]-85 was delayed by M in sequence.
I was worried about the meeting, and Figure 7 shows -521-N. 21-N+1.・In the state shown in FIG.
When 5 is simultaneously applied to each phase determination circuit 17-1 to 37-86, each output selection pulse 22-1 to 22-35 becomes -f.
The reset pulse 26Vi, which is served as the output signal of the Nantes gate 18, is supplied with output selection pulses 22-1 to 22-fl16 in parallel. Level "("")
Accordingly, each of the phase determination circuits 17-1 to 17-i3R has input delay control circuits 111-1 to 111-11.
If the clock pulse rises at -35, that i! A state is reached in which a one-time delay clock signal can be passed through 11 thousandths of a time. Note that the phase determination set pulse 2IS is, for example, one of the pulses in the clock run-in OR, which is the above-mentioned 17 bit synchronization signal in the received character information signal, or is accurately phase-synchronized with the framing code FC. (7
Therefore, the reset pulse 26 obtained as the output signal of the digital input signal 18 is exactly in phase with the input digital signal. At the same timing, the logic level becomes 10'', and all the determination circuits 17-1 to 17-35 stop phase determination when the next set pulse 25 arrives. Delayed lock wound”
Each of the phase determination circuits 17-1 to 17-1 is in a state where the signal can pass through.
17-85, a clock pulse rises to the forging tip after the set pulse 2B is applied. In the illustrated example, a delayed clock signal -@121-N+8 is supplied (and a phase determination circuit 17-85 is supplied).
4 output select pulse 28-N+8 returns to a low logic level 10'' upon the rising edge of the clock pulse in input delayed clock signal 21-N+8, as shown in FIG. Since a low logic level "0" is generated, the NAND output and the reset pulse 26 at 17 become a high logic level @1", so that only the phase determination circuit 17-N+3 detects the manually delayed clock signal 21-N+8. Maintaining a passable state, the 7th
Although the trap output clock IM number 2δ-N+8 is obtained as shown in the figure, the other phase determination circuits 17-1 to 17-N+2 and l2N+4 to 1f-85 each have their respective output selection pulses as shown in FIG. High #i71 logic level ″″l as shown in
'', and each input delay clock pulse 2]-1 to 21-N+2 and 21-N+4 to 2l
-35F'i cannot be passed through, and as shown in FIG. Output clock signal 2..8;, -1 to 28-..., 1 From the OR gate 19 using human power as 35, the judgment? circuit 17
-N+8 output output fF! Set pulse 25 whose phase is precisely synchronized with the human code signal generated by No. i 18-N+21
After the application of , the clock signal 21-N+8 that rises first is extracted as an OR output, and the phase difference between the phases ti of the delayed clock signal group obtained from the delay line 16 is 5 n8
'i A recovered clock signal 24 having a high phase synchronization IrfI complex with a maximum phase difference is obtained. Accordingly, the phase determination circuit 1 in the circuit configuration shown in the lower part of FIG.
Examples of the true structure of 7 are shown in FIGS. 8 and 9, respectively. In the configuration example shown in FIG. 8, the set pulse 25
With the application of
Therefore, the selection pulse 22 consisting of the respective Q output becomes the high logic level "1". As mentioned above in FIG. Low-salt level 10'', so
The gate output of the exclusive OR gate 2) which receives the reset pulse 2i4 "0" and the Q output "0" becomes the low-salt level "0'' at the same time as the set pulse 25 is applied. In such a state, when the clock pulse of the input delayed clock signal 21 rises and the clock input terminal 0K4i [level 113'' of the flip-flop 28 is applied, the data input terminal becomes a low logic level 10'' due to the output of the OR gate 27. Therefore, the Q output becomes a low logic level "0" and the Q output becomes a high logic level "]
”, and the AND gate 29 that led to the Q output 11”
7, the input delay clock 18 and 21 are taken out as a selective output candle 11428. - The output of the Nantes gate 18 in the illustrated configuration that led to the Q output "0" becomes the logic level "1", so the gate output ""] is set to the reset pulse 26
The 10,000 inputs of the exclusive or gate 27 led as Holding a low logic level 10'' and thus responding to the application of the cent pulse 26, the flip-flop 88 of the phase decision circuit A will remain low even with the application of the cent pulse 26 from the Nant gate 18. The state does not change and the phase determination circuit 17 continues

[7] The selected output clock signal 28 is taken out. After applying the set pulse 25 and before the clock pulse of the input continuous firing clock signal 21 rises, the exclusive OR gate 27 to which the high-salt level ``]'' of the reset pulse 26 is added as described above. In the other phase-fixing circuit 17, the Q output becomes a low logic level "0" in response to the application of the set pulse 25, and the Q output ""
0'' is applied as the other input to the exclusive OR gate 27, so the output of the exclusive OR gate 27 is a high logic L'
Since the input terminal of the flip-flop 28 becomes a high logic level 1], the clock pulse of the input delayed clock signal 21 applied to the clock input terminal C rises and becomes a logic level. Even if it becomes “1”,
The state WA of Q output 11'' and Q output ``0'' does not change, leading to its Q output 1o'', and since the 9 output AND gate 29 is closed, its phase 4! l] The output selection clock signal 28 cannot be served from the constant circuit 1f. In another configuration example of the phase determination circuit 17 shown in FIG. 8(
The Q output at 3.81 is set to a high logic level "1", and the Q output is set to a low logic level "0". (7 Therefore, the reset pulse 26 as the output of the Nant gate 18 in the configuration shown in FIG. Apply reset pulse g6 1. The data input terminal of the flipflop 80 is low.
The salt level becomes 10". Therefore, in the Frisogeflock 80, the clock pulse of the input delay clock gI, which is 2, supplied to the clock input terminal G rises to 1". According to the level “0” of the data input terminal, the Q output is high-salt level “1”.
becomes. The Q output of the flip-flop 80 is fixed to the low logic level @0'' by grounding the data input terminal to the 7-tube 70-tube δ1 that supplies the Q output @] to the clock input terminal O. Q according to the rise of “1”
The output becomes a low logic level 10'', and the Q output becomes a high logic level ``1''. Therefore, the Q output of the flip-flop δO, which supplies its Q output 10'' to the reset input terminal R, becomes a high logic level. The flip-flop maintains the level "1" level m4 and supplies its high logic level "1" to the clock input terminal 0; the other Q output also maintains the "l!+-salt level 11" state (2 , the AND gate 29d to which the Q output 11'' is applied remains open until the next set pulse 215 is applied to set the frisogeflock δ1 and its Q output reaches the low-salt level @0''. , the input delayed clock signal 21 is passed through and taken out as the output selection clock signal g8.
Holding the state WA at '1'', 1i does not respond to the rising edge of the subsequent clock pulse of the input delayed clock signal 21 applied to the clock input terminal 0, and the AND gate 29 is held 11 without being opened. In other phase determination circuits in which the reset pulse 26 becomes a high logic level "1" before the rising edge of the clock, the Q output of the flip-flop 80 remains at a low logic level even when the rising edge of the input delayed clock signal 81 arrives. The Q output of the flip 70 knob δ1 is low -
The salt level "0" is maintained in the casing, and gate 29Fi
It becomes a closed l case, and the output selection clock signal is not used. As is clear from the above description, according to the present invention, for example, when reproducing the O1 Click Walk No. Without using a read-only memory, it is possible to regenerate a clock signal with a relatively simple configuration, even with a phase difference between M1 and 1. It is also easy to configure it with a circuit.The clock regeneration method of the present invention not only provides the above-mentioned special effects when applied to the reception of teletext broadcasts broadcasted on the above-mentioned nine character information signals 4Ij11r. , fax +
) It can be similarly widely applied to other broadcasting systems that multiplex transmit digital information signals, such as Takame broadcasting. In addition, the clock cannot be regenerated, which conventionally occurred due to the input conditions of the only memory. There is also a delay that occurs immediately after the application of a set pulse that is consistent and precisely phase-synchronized with the high-power code signal. The phase-period of the recovered clock is 4M by only the delayed phase of the clock pulse.
Since it is a conductor, stable and reliable locking operation can be achieved without having to interact with other circuits, and the circuit configuration can be simplified.

[Brief explanation of the drawing]

Fig. 1 is a signal waveform diagram showing the structure of a character information @ signal data packet, Figs. 2 to 4 are block diagrams each showing an example of the structure of a four-track reproducing circuit according to the conventional method, and Fig. 6 is a signal waveform diagram showing the structure of a character information @ signal data packet. A block diagram showing a configuration example of a clock generation circuit according to the present invention; FIGS. 6 and 7 are signal waveform diagrams showing all waveforms of each part of the clock reproduction circuit; FIG. 8 FIG. 9 is a block diagram showing an example of the phase determining circuit W4tli in the clock reproducing circuit. l・Gate circuit, 2・Ringing circuit, δ・216
Mm wire with tag, 7 latch circuit, 8 read-only memory, 9...data selector, 1 ma...phase determination block, 17-1 to 17-85...phase-t4J short circuit,
18 Nantes gate, 19... OR gate, 27 Exclusive OR gate, gS, δ0°81... Flip flop 7', 29 Unh' Kate. Fig. 6 Fig. 71'・ζ1 530- Fig. 8 Fig. 9

Claims (1)

[Claims] In reproducing the reconnaissance lock M corresponding to the code signal in the above f8 based on the bit synchronization wander code included in the received signal, the Ail g+Nibinoto synchronization one bit The same repetition as the number [if one frequency is all seven, the phases of the VC and each other are seven)] The rise time of the clock signal of the counting, the generation time of the pulse that is phase-synchronized with the above-mentioned hit synchronization signal, and the respective times. n continuation (7, Hinu shift, previous 6 bales of clock signals, rises first when the pulse occurs) (1, set the clock signal to West IJ Me small number clock 18~ A clock writing system featuring: