JPH0246034A - Data multiplexer - Google Patents

Abstract

PURPOSE:To thin a specific bit out of information bits constituting data and to easily vary a transmission speed by adding a clock thinning circuit for thinning a data transmitting clock to constitute a variable data clock to a data multiplexer. CONSTITUTION:The clock thinning circuit 12 for thinning a data clock 8 from clocks generated from a clock generating circuit 10 is connected. Since quite the same operation as that of an ordinary device should be executed when a data transmission speed selecting signal 11 is ON, the circuit 12 outputs the data clock 8 generated from the circuit 10 as a variable data clock 12 without changing it and data are inputted at the same speed as the ordinary data transmission speed. When the signal 11 is turned off, the circuit 12 is driven and only the clock required at the time of inputting the leading bit of the data 5 e.g., is thinned. Thereby, only five bits in an information bit 2 consisting of apparent six bits are used, so that 5/6 times the ordinary data transmission speed can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data multiplexing device for data transmission.

[Conventional technology]

Figure 3 shows, for example, CCITT Recommendation X, 50-PIG.
UREI/X.

50 (1985), in which (11 is the F bit for synchronizing data, (2) is an information bit, (3) is a control signal, etc. In addition, Fig. 4 is a diagram showing a circuit configuration for realizing the principle shown in Fig. 3 above. (6) is the first shift register that inputs data (5) in 6 bits serially and outputs it in parallel; (7) is the information bit from shift register (6) and the F bit (
11. Second shift register with S bit (3) as parallel input, (8) is data clock for data (5), (9) is envelope clock for reading shift register (7), θ [ is a clock generation circuit that generates a data clock (8), an envelope clock (9), and an F bit <11.

Next, the operation will be explained. Data (5) from the terminal is read into the shift register (6) by the data clock (8) from the clock generation circuit α. When 6 bits of information bits (2) are manually input to the first shift register (6), they are transferred in parallel to the second shift register (7), and at the same time F bits are transferred from the clock generation circuit αΦ and also as a control signal. , reads the S bit (3).

Next, the envelope clock (9) (in this case, 876 times the frequency of the data clock (8)) is read out serially from the second shift register (7), resulting in data as shown in Figure 3. Composition - becomes a so-called envelope.

[Problem to be solved by the invention]

Since the conventional data multiplexing device is configured as described above, the data (5) from the terminal is fixed at the speed of the data clock (8), and the data clock (8) is The speed is fixed (determined by the configuration of the multiplexer). That is, the speed of the data clock (8) is fixed, and the transmission speed of the data (5) cannot be changed.

This invention was made to solve the above-mentioned problems, and aims to provide a data multiplexing device that can vary the transmission speed of data (5) when multiplexing data. purpose.

[Means to solve the problem]

The data multiplexing device according to the present invention has an additional clock thinning circuit that thins out the clock for data transmission to produce a variable data clock.

[Effect]

The data multiplexing device according to the present invention is constructed by thinning out specific bits from among the information bits constituting data by a variable data cropter, thereby making the data transmission rate variable.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, θυ is a data transmission speed selection signal, (2) is a clock thinning circuit that thins out the data clock (8) from the clock generation circuit Ol, and α is a variable data clock created by the clock thinning circuit.

The operation will be explained below. Data transmission rate selection signal, CCCITT recommendation v, 2 recommendation path 111) QD is ON
In this case, it is necessary to operate exactly the same as the conventional device, so the clock thinning circuit (b) outputs the data clock (8) from the clock generation circuit O1 as it is as a variable data clock α, and then outputs the data clock ( 5) is input at the same data transmission rate as before.

Next, when the data transmission rate selection signal αD turns OFF,
The clock thinning circuit ano operates, for example, data (5)
Only the clock when manually inputting the first bit of the data is thinned out. Due to this operation, there are apparently 6 information bits (2)
Only 5 bits of the data are used, resulting in a 576-fold increase in data transmission rate.

The state of multiplexing at this time is shown in Figure 2. In this figure, the bits marked with X are bits that are not multiplexed because the variable data clock AL that has been thinned out is used by the clock thinning circuit (2). represents.

Comparing this figure with FIG. 3, it can be seen that multiplexing is performed for a transmission rate of 5/6.

In the above embodiment, a case was shown in which the output of the clock thinning circuit @ is directly output as the variable data clock α list, but a phase lock loop (PLL) etc. is provided here, and the output of the variable data clock a31 is It may be configured so that the duty ratio of is 1:1.

Although an example is shown in which 0 clock decimation circuits are used for 6 clocks and 1 clock, other decimation ratios may be used. In particular, in the case of decimation of 3 clocks for 6 clocks,
1/2) A similar effect can be obtained as a frequency dividing circuit.

〔Effect of the invention〕

As described above, according to the present invention, since the data multiplexing device is capable of varying the data transmission rate, there is an effect that the transmission rate can be easily varied.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a data multiplexing device according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a transmission signal of the present invention, FIG. 3 is a configuration diagram of a transmission signal of a conventional data multiplexing device, and FIG. FIG. 4 is a circuit diagram of a conventional data multiplexing device. (1) is F focus, (2) is information bit, (3) is S bit, (4) is thinned bit, (5) is data, (
6) is a shift register, (7) is a shift register, (8
) is a data clock, (9) is an envelope, θe is a clock generation circuit, Qυ is a data transmission speed selection signal, (b) is a clock thinning circuit, and 01 is a variable data clock. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Figure 2 613 False orthography (self-motivated) Hantou April 7411 t1°Heo Commissioner's Palace 4. Display of the case Patent application No. 3, Figure 2, Name of the invention, Data multiplexing device, Representative of the person making the amendment, Figure 4, Section 5, Subject of amendment (1) Detailed description of the invention in the specification, column 6, Amendment (1) The description is amended as follows.

Claims (2)

[Claims] (1) A clock generation circuit that generates a predetermined data clock based on a data transmission speed selection signal from a terminal, etc., a clock thinning circuit that thins out this data clock to create a variable data clock, and the number of bits corresponding to this variable data clock. A first shift register that takes in data, a parallel data output of this first shift register, an F bit for data cycle from the clock generation circuit, and an S bit for the data transmission speed selection signal constitute one envelope. A data multiplexer equipped with a shift register that outputs (2) A phase-locked loop is provided at the clock thinning circuit output, and the duty ratio of the variable data clock output is set to 1.
2. The data multiplexing device according to claim 1, wherein the data multiplexing device has a 1:1 ratio.