JPH03240143A - Method and device for switching address counter clock - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by providing an operation clock switch means which switches the operation clock of a counter in response to the clock of the input/output data to be applied to a RAM. CONSTITUTION:An operation clock switch circuit 1 outputs an operation clock 4 to a counter 2 and switches (n) types of clocks 4 in response to the clock of the input/output data applied to a RAM 3. In other words, the circuit 1 switches the clocks 4 with change of the clock of the input/output data. An address 5 is outputted from the single counter 2 and therefore the continuous changes are kept despite the change of the clock 4. Thus the circuit scale is reduced and the access speed can be slowed down for the element of the RAM 3.

Description

[Detailed description of the invention] and equipment.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional example.

The input/output data 6 to the RAM 3 changes depending on n types of clocks. In order to output continuously changing addresses to the RAM 3 in accordance with the n types of clocks, n types of counters 9, 10, 11 . and the operation clocks 14, 15, 16 to the respective counters 9, 10, 11.
An n-stage selector 13 that selects the counters 9, 10, and 11 and a counter selection circuit 12 are activated according to the operation clock generation circuit 7 that generates the input/output data, and the clock of the input/output data changes. Also, a count value-number circuit 8 is required to make the address change continuously.

[Problem to be solved by the invention]

The conventional address counter clock switching device requires (1) counters 9, 10, and 11 for each type of clock generated from the operation clock generation circuit 7, resulting in a large circuit size.

(2> Since the N-stage selector 13 is required between the counters 9, 10, 11 and the RAM 3, the delay becomes large.

(3) A count value-number circuit 8 is required to always set the address to the RAM as a continuous value, and a counter selection circuit 12 is required to change the input/output data clock. Control becomes complicated.

There is a drawback.

[Means to solve the problem]

The address counter clock switching method of the first invention is R
When an address to the AM is generated by a counter and input/output data to the RAM is changed by n different clocks, a counting procedure for outputting the address to the RAM and the RAM, and an operation clock for the counter as described above. The operating clock switching procedure is configured to switch according to the clock of input/output data to/from the RAM.

The address counter clock switching device of the second invention is R
When an address to the AM is generated by a counter and the input/output data to the RAM changes according to n different clocks, the RAM and a counting means for outputting the address to the RAM; The operating clock switching means switches according to the clock of input/output data to/from the RAM.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The operating clock switching circuit 1 outputs an operating clock to the counter 2, and switches among n types of operating clocks 4 according to the input/output data tarok. Counter 2 is an address counter of RAM3. RAM3 is random access memory. The operating clock 4 is an operating clock selected by the operating clock switching circuit 1. This is the address of RAM3 output by address 2.

Assume that counter 2 is now counting based on operation clock 4 and outputting address 5.

Next, assume that the input/output data clock changes. Then, the operating clock switching circuit 1 switches the operating clock 4 according to the input/output data clock. Since the address 5 is output from only one counter 2, continuous change is maintained even if the operating clock 4 changes. By repeating the same process, the operation clock switching circuit 1 and the counter 2 operate in the same manner for the clocks of n types of input/output data.

〔Effect of the invention〕

As explained above, the present invention generates an address to the RAM using a counter, and when there are n types of clocks for input/output data to the RAM, the circuit size is reduced by switching the operating clock of the counter. This has the effect of slowing down the access speed of the RAM elements.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example.

1...Operating clock switching circuit, 2...
Counter, 3...RAM, 4...Operating clock, 5...Address to RAM, 6...
...Input/output data to RAM, 7...Operation clock generation circuit, 8...Runt value matching circuit,
9-11...Counter, 12...Counter selection circuit, 13...N-stage selector, 4-1
6...Operating clock, 17...Address.

Claims (1)

[Claims] 1. Generate an address to the RAM with a counter and
When the input/output data to the AM changes according to n different clocks, the RAM and the counting procedure of outputting the address to the RAM, and the operation clock of the counter according to the clock of the input/output data to the RAM. An address counter clock switching method comprising: an operation clock switching procedure. 2. Generate an address to the RAM with a counter and write the address to the R
When the input/output data to the AM changes according to n different clocks, the RAM and the counting means for outputting the address to the RAM, and the operation clock of the counter according to the clock of the input/output data to the RAM. 1. An address counter clock switching device comprising: operation clock switching means for switching.