JPH0575414A - Data selection circuit - Google Patents

Abstract

PURPOSE:To realize a data selection circuit for processing a digital signal in which the difference of the propagation delay time of data between the input and output is small and a difference from the propagation delay times at the time of switching is decreased. CONSTITUTION:This data selection circuit is provided with an inversion means 10 inverting a selection signal S used for selecting input data, a 1st data passing means 20 passing the input data D1 with the selection signal S, a 2nd data passing means 30 passing input data D2 with an output resulting from inverting selection signal S with the inversion means 10 and an OR means 40 ORing the output of a 1st data passing means 20 and the output of a 2nd data passing means 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data select circuit for digital signal processing. In digital signal processing, high speed operation is required in order to perform various calculations in real time. In such digital signal processing, a large number of data select circuits that select and output one of the two input signals D1 and D2 according to the designation of the selection signal S are used.

The data select circuit is required to have a small propagation delay time and have the same propagation delay time regardless of which of the two paths is selected.

[0003]

2. Description of the Related Art FIG. 4 shows a diagram for explaining a conventional example. In the figure, 11 is an inverter that inverts the selection signal S, 21A is a flip-flop circuit that holds the input data D1 with the clock signal CK (hereinafter referred to as F / F circuit), and 31A is the input data D2 that is held with the clock signal CK. F / F circuit, 41A is an OR circuit (hereinafter referred to as OR circuit) 4
2, 43 and a logical product circuit (hereinafter referred to as an AND circuit)
A selector composed of 44, and 51 is an F / F circuit which holds the output of the selector 41A by the clock signal CK.

In the above circuit, for example, the selection signal S
Is “1”, “0” inverted by the inverter 11 is input to one input terminal of the OR circuit 42, and the OR circuit 4
Since the input data is input to the other input terminal of 2,
The input data D1 is directly output from the output terminal of the OR circuit 42. On the other hand, “1” of the selection signal S is the OR circuit 4
3 is input to one of the input terminals of the OR circuit 43, so that the output terminal of the OR circuit 43 is always "1" regardless of the input data D2.
Is output.

Therefore, by ANDing the output of the OR circuit 42 and the output of the OR circuit 43 with the AND circuit 44, the input data D1 is output from the selector 41A. When the selection signal S is "0", "1" is O
Input to one input terminal of the R circuit 42, and "0" is OR
Since it is input to one of the input terminals of the circuit 43, the AND circuit 44 takes the logical product of the output of the OR circuit 42 and the output of the OR circuit 43 to output the input data D2 from the selector 41A.

[0006]

The OR-AND type selector used in the above-mentioned conventional example has a large propagation delay time, and there is a difference in the propagation delay time depending on the path for selecting data.

Therefore, when a high-speed operation is required, a sufficient setup margin cannot be secured, and there is a problem that the setup margin changes due to switching of the selector.

The present invention intends to realize a data select circuit which can reduce the data propagation delay time between input and output and reduce the difference in propagation delay time at the time of switching.

[0009]

FIG. 1 is a block diagram for explaining the principle of the present invention. In the figure, 10 is an inverting means for inverting the selection signal S for selecting the input data, 20 is a first data passing means for passing the input data D1 by the selection signal S, and 30 is an inverting means for the selection signal S. Reference numeral 40 denotes a second data passing means for passing the input data D2 by the output inverted at 10, and 40 denotes the first data passing means 20.
Of the second data passing means 30 and the output of the second data passing means 30.
The data passing means 20 and the second data passing means 30 block the data which is not passed, and the logical sum means 4
When 0, the output of the first data passing means 20 and the output of the second data passing means 30 are ORed to perform data selection.

Further, F / F circuits 21 and 31 are used as the first data passing means 20 and the second data passing means 30, and the selection signal S is input to the F / F circuit 21 in the same phase. , The F / F circuit 31 is inverted to input the selection signal S, and the outputs of the F / F circuits 21 and 31 are ORed to form a data select circuit.

Further, the first data passing means 20 and the second data passing means 20
As the data passing means 30, the AND circuits 22 and 32 are used to form a data select circuit.

[0012]

The selection signal S of the input data is inverted by the inverting means 10, the selection signal S is input to the first data passing means 20 in the same phase, and is inverted to the second data passing means 30. The selection signal S is input.

The first data passing means 20 has a selection signal S.
Input data D1 is passed when is at "low" level,
The second data passing means 30 passes the input data D2 when the inverted selection signal S is "low" level, that is, when the selection signal S is "high" level.

In this state, the logical sum of the output of the first data passing means 20 and the output of the second data passing means 30 is obtained by the logical sum means 40, so that the propagation delay time of the data from the input to the output can be calculated. It can be made small, and the difference in propagation delay time can be made small even if the output data path is switched.

[0015]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
In the figure, 11 is an inverter as the inverting means 10 described in the principle diagram, and 21 is an F as the first data passing means 20.
/ F circuit, 31 is an F as the second data passing means 30
/ F circuit, 41 is an OR circuit as OR means 40, 5
Reference numeral 1 is an F / F circuit for outputting data.

In the configuration of the above embodiment, the F / F circuit 21
The selection signal S is input to the reset terminal R of the above, and the inverted selection signal S is input to the reset terminal R of the F / F circuit 31. Therefore, when the selection signal S is "1", the F / F circuit 2
1 is not reset and becomes normal operation, and input data D1
Since the F / F circuit 31 is reset by the inverted selection signal S, the input data D2 is blocked and "0" is always output.

In this state, the logical sum of the outputs of the F / F circuit 21 and the F / F circuit 31 is calculated to obtain the input data D1.
Is output. On the contrary, when the selection signal S is "0", F /
The F circuit 21 is reset, and the input data D2 input to the F / F circuit 31 is output from the OR circuit 41.

The F / F circuit 51 holds the output of the OR circuit 41 by the clock signal CK and outputs it. FIG. 3 is a diagram for explaining another embodiment of the present invention. Inverter 11, F / F circuits 21, 31, OR circuit 41,
The F / F circuit 51 has the same structure as that described in the embodiment of FIG.

Reference numerals 22 and 32 respectively denote F / F circuits 21 and
The AND circuit is connected to the input terminal of 31 and passes the input data to the F / F circuits 21 and 31 by the selection signal S.

The F / F circuits 21 and 31 have the same structure as described in the embodiment of FIG. 2, but the reset terminal R is not used here. In the configuration of FIG. 3 described above, when the selection signal S is "1", the AND circuit 22 outputs the input data D1, the AND circuit 32 always outputs "0" by the inverted selection signal S, and F / Input data D1 is output by taking the logical sum of the outputs of the F circuit 21 and the F / F circuit 31.

On the contrary, when the selection signal S is "0", AN
The D circuit 22 always outputs “0”, the AND circuit 32 outputs the input data D2, and the F / F circuit 21 and the F / F circuit 3
By taking the logical sum of the outputs of 1, the input data D2 is output.

[0022]

By inputting two input data to the F / F circuit and controlling the output of the data by the F / F circuit,
It is possible to realize a data select circuit that can reduce the propagation delay time, can reduce the difference in the propagation delay time even when the output data is switched, and can secure an operation margin.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram illustrating another embodiment of the present invention.

FIG. 4 is a diagram illustrating a conventional example.

[Explanation of symbols]

 10 Inversion Means 11 Inverter 20 First Data Passing Means 21, 21A, 31, 31A, 51 F / F Circuits 22, 32, 44 AND Circuit 30 Second Data Passing Means 40 Logical Or Means 41, 42, 43 OR Circuits 41A selector

Claims (3)

[Claims] 1. A circuit for selecting and outputting any one of two input data (D1, D2), and an inverting means (10) for inverting a selection signal (S) for selecting the input data, and the selection. The input data (D2) is passed by the first data passing means (20) which passes the input data (D1) by the signal (S) and the output obtained by inverting the selection signal (S) by the inverting means (10). Second data passing means (30), an output of the first data passing means (20), and the second data passing means (30)
And a logical sum means (40) for taking a logical sum of the outputs of the data passing means (30). 2. The first data passing means (20),
2. The data select circuit according to claim 1, wherein the second data passing means (30) comprises a flip-flop circuit (21, 31). 3. The first data passing means (20),
The second data passing means (30) is connected to the AND circuit (2
2. The data select circuit according to claim 1, wherein the data select circuit is composed of