JPS5935453B2 - Interrupt priority determination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a priority determining circuit for interrupt processing in an information processing system.

Conventionally, this type of interrupt priority determination circuit has a plurality of interrupt request signals EventA to EventA, as shown in FIG.
H is temporarily stored in D-FLIPFLOP by clock φ1, the output of this D-FLIPFLOP is input to an AND circuit according to a predetermined priority order, and the result is stored in D-FLIPFLOP by clock φ2. It has been realized.

Therefore, since the priority order is determined by the AND circuit, there is a drawback that when it is desired to change the priority order by the system, this request cannot be realized. For example, the priority order may be changed because at least one of the eight terminal devices is changed and another terminal device is connected.
In this case, the logic circuit had to be rearranged. The present invention provides a memory circuit for storing priority information given by an instruction instead of an AND circuit that determines priorities, performs a logical operation on an interrupt request signal and the output of the memory circuit, and uses this result as a memory circuit. Therefore, it is an object of the present invention to provide an interrupt priority order determining circuit that can arbitrarily change the priority order by determining the priority order. The present invention has n fields provided corresponding to each of the n (n≧2) interrupt request signals, and each of the n fields corresponds to the n interrupt request signals. Priority information consisting of n bits of priority indication bits provided corresponding to each signal is stored, and the interrupt request signal is assigned a priority lower than the priority of the interrupt request signal corresponding to the field. The corresponding bits include n memory circuits for storing n pieces of priority information assigned one of the binary states, and a memory circuit corresponding to each arbitrary field of the n pieces of priority information. n first AND circuits for calculating an AND of an interrupt request signal and a priority instruction bit corresponding to the interrupt request signal for each of the interrupt request signals; Each of all other interrupt request signals except for the interrupt request signal and the priority instruction bit corresponding to each of these interrupt request signals are NANDed for each of these interrupt request signals. (n-1) NAND circuits, the output of the first AND circuit for each arbitrary field, and the output of the n-1 NAND circuits. and n second AND circuits that output two interrupt signals, and the n priority AND circuits output from the n second AND circuits in response to the n interrupt request signals. This is an interrupt priority determining circuit characterized in that it outputs an interrupt signal with a set priority.

Next, one embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 2, the first embodiment of the present invention inputs eight interrupt request signals EventA to EventH, stores the states of EventA to EventH at clock φ1, and provides E-E as the output. Buffer register FA
IO and 8-bit priority information PIA-PIH are input, and PIA-PI is set by the set signal SA-SH.
Memory circuit MAll and memory circuit MB that store the state of IH
l2, memory. The eight memory circuits that characterize the present invention, the circuit MCl3, the memory circuit MDl4, the memory circuit MEl5, the memory circuit MFl6, the memory circuit MGl7, and the memory circuit MHl8, the output of each memory circuit, and the output of the buffer register FAlO EA- Eight logical operation circuits GAl9, GB2O,
GC2l, GD22, GGE23, GF24, GG25
, GH26, and a buffer register FB27 which inputs the output GA-GH of each logic operation circuit and stores the state of GA-GH at clock φ2.

Referring to FIG. 3, the buffer register FAlO is composed of eight D-flip-flop circuits 101 to 108, and the relationship between the interrupt request signal and the output is EventA-108.
EA, EventB-EB, ...EventH
-EH. Referring to FIG. 4, the memory circuit MA
ll is eight D-flip-flop circuits 109 to 116.
The priority information and output relationship are PA MA, PI-MA, ... PI-MA, respectively, and A
'BB' HH is here.

In addition, the logic operation circuit GAl9 includes an AND gate circuit 117 inputting EA and MAA, and EB (5MAB, E0 and M
Nandgate circuits 118 to 12 whose inputs are AO, EO and MAO, EE and MA, E (!-MA, E and MA, E (!l: MAE'FF'GO' HH)
4 and an 8-input AND gate circuit 125 which receives the outputs of each gate circuit as inputs.

Referring to FIG. 5, the buffer register FB27 is composed of eight D-flip-flop circuits 126 to 133.Each output GA of the eight logic operation circuits GAl9 to GH26 is shown in FIG.
-GH as input and corresponding output, that is, interrupt signal Ev
Give enta-Eventh.

The logic operation circuits GB2O to GH26 are also similar to GAl9. However, the output E of buffer register FAlO
The outputs MXY(X
and Y indicates B-H), the gate circuit will be MX
If OI)

In the memory circuits MAll to MHl8, priority information for Event A is stored in MAll and priority information for Event B is stored in MBl2 in advance according to a command from the information processing device.

Similarly, interrupt request signals E are also sent to MCl3 to MHL8 respectively.
Priority information for eventC-EventH is stored. Figure 6 shows the interrupt request signal EventA-Even.
Memory circuits MAll to M when assuming the priority order of tH
This shows the correspondence between Hl8 and stored priority information.

Referring to FIG. 4, when MAA is at the logic value ``0'', G becomes the logic value 10'5 and H''A regardless of the states of EA-EH(c)?? and MA3-MA.

Therefore, the D-flip-flop circuit 116 outputting MAA performs control to specify whether or not to permit or disable acceptance of the interrupt request signal EventA. In order for MA to have a logical value of 11'' and E to have a logical value of 11'2, and AA and G to have a logical value of 01'', NAND gate A circuit 118 to NAND gate circuit 124 are required.
The outputs of all NAND gate circuits must have a logic value of 11''.

In order for the NAND gate circuit output to have a logical value of 11'2,
The output of the D-flip-flop, which is the input, is the logical value Tt.
It must be in the state of ``O'' or the corresponding E-E must be in the logical value ``0'' and become AH.

Therefore, for example, if MA has a logic 0B value of 10'2, even if E has a logic value of Ttl'2, the NAND B gate circuit 118 can provide a logic value of Ttl'5 as an output.

Conversely, when the logical value is 01'', if EB is not the logical value 0, the logical value Ttl'' of the output of the NAND gate circuit 118
can't get it. From this, the D-flip-flop circuit 115 specifies and controls whether the interrupt request signal EventA has a high priority or a low priority with respect to the interrupt request signal EventB. Similarly, the D-flip-flop circuit 114 receives the interrupt request signal EventC, and the D-flip-flop circuit 113 receives the interrupt request signal E.
D-flip-flop circuit 112 for ventD
is for the interrupt request signal EventE, the D-flip-flop circuit 111 is for the interrupt request signal EventF, and the D-flip-flop circuit 110 is for the interrupt request signal Ev.
The D-flip-flop circuit 109 for entG specifies and controls the priority level of the interrupt request signal EventH relative to the interrupt request signal EventA.
Similarly, the memory circuit MBl2 receives the interrupt request signal Even.
Controls the priority levels of tB and other interrupt request signals Event and designates whether to permit or prohibit acceptance of the interrupt request signal EventB. Hereinafter, for other storage circuits, other interrupt request signals E will be
It controls the priority level with respect to the event and designates whether to allow or prohibit reception. In this way, the interrupt request signal EventA is generated with the priority information stored in the memory circuit in advance.
- When EventH is input, the interrupt signal with the highest priority among the enabled interrupt signals and the signals with a logic value of "1" is sent to the output of the buffer register 27 with a logic value of "1".
By changing the priority information stored in the memory circuit, the priority order of the interrupt signal can be arbitrarily determined.

[Brief explanation of drawings]

FIG. 1 is a conventional interrupt priority determining circuit, FIG. 2 is a schematic diagram of a first embodiment of the present invention, FIG. 3 is a detailed diagram of buffer register FAlO shown in FIG. 2, and FIG. The figure is the second
The memory circuit MAll and the logic operation circuit GA illustrated in the figure
FIG. 5 is a detailed diagram of the buffer register FB27 shown in FIG. 2. EventA-EventH...Interrupt request signal, Eventa-Eventh...Interrupt signal,
PIA-PIH...Priority information, 10...
...Buffer register, 11-18...Memory circuit, 19-26...Logic operation circuit, 27...
・・・Basshua register.

Claims (1)

[Claims] 1 has n fields provided corresponding to each of the n (n≧2) interrupt request signals, and each of the n fields corresponds to each of the n interrupt request signals. A bit corresponding to an interrupt request signal that stores priority information consisting of n-bit priority instruction bits provided corresponding to the field, and is given a lower priority than the priority of the interrupt request signal corresponding to the field. includes n memory circuits that store n pieces of priority information assigned one of the binary states, and an interrupt request corresponding to each arbitrary field of the n pieces of priority information. n first logical product circuits that calculate a logical product of a signal and a priority instruction bit corresponding to the interrupt request signal for each of the interrupt request signals; and an interrupt request corresponding to each of the arbitrary fields. n(n−
1) AND the output of the first AND circuit and the output of the n-1 NAND circuits for each arbitrary field, and generate one interrupt signal for each field. n second AND circuits that output n interrupt request signals; An interrupt priority determination circuit characterized in that it outputs an interrupt signal.