JP3166193B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit using a field programmable gate array.

[0002]

2. Description of the Related Art Conventionally, a field programmable gate array (hereinafter referred to as an FPGA) has been proposed in which various logic circuits can be formed by changing internal connections by a configuration program (for example, US XIL).
INX: product number XC2000). Since the FPGA forms a logic circuit based on a configuration program loaded from the outside, that is, configuration information such as logic combination data and connection information, a conceptually dynamic configuration change is possible.

FIG. 5 shows an example of using a conventional FPGA. Conventionally, a logic circuit 53, a PROM 55,
57 and 59 are used in combination. The logic circuit 53 is a circuit combining an AND circuit and an OR circuit. The PROMs 55, 57, and 59 store microcodes constituting different configuration programs. In the above configuration, when the internal status information of the FPGA 51 and a request signal from the outside are input to the logic circuit 53, the logic circuit 53 uses the PROMs 55 and 57 with logic preset according to the internal status information and the request signal from the outside. , 59, one PROM is selected. And the selected PROM
FP to store configuration program
The data is serially transferred to the built-in memory of the GA 51. In this way, the FPGA 51 can load the configuration program and form a predetermined logic circuit A.

[0004]

However, although the conventional FPGA 51 is conceptually capable of dynamically changing the configuration, it has a problem that it is practically poor in versatility. This is because, conventionally, the configuration program must be serially transferred to the FPGA 51, and the overhead, that is, the time required for rewriting the program becomes longer. Conventional FPGA 51
In this case, the overhead is too long, and it is substantially impossible to proceed with processing while dynamically changing the configuration. For example, if a process involving a change in a logic circuit can be executed in the middle of a process, such as a process with a conditional branch, the versatility of the FPGA 51 is greatly improved. It is not practical for long.

An object of a semiconductor integrated circuit according to the present invention is to solve the above-mentioned problems and to realize a semiconductor integrated circuit having a short overhead of an FPGA and a high versatility.

[0006]

According to the present invention, there is provided a semiconductor integrated circuit, comprising: a field programmable gate array for changing a connection state inside by a loaded microcode to form a logic circuit determined by the microcode;
The internal status information of the field programmable gate array and a request signal from the outside are input, and the next micro-cell to be loaded by the field programmable gate array based on a logic set in advance according to the internal status information and the request signal from the outside. A logic circuit that determines a code and outputs a next microaddress signal indicating the determined microcode, a decoder that decodes a next microaddress signal output from the logic circuit and selects the next microcode, and a plurality of microcodes. Microcode storage means for storing and outputting the microcode selected by the decoder to the field programmable gate array, the field programmable gate array, the logic circuit, and the decoder , The fit and the microcode storage means to one package, characterized in that connected between said field programmable gate array and the micro-code storage means in parallel.

In the semiconductor integrated circuit having the above configuration, internal status information of the field programmable gate array and a request signal from the outside are input to the logic circuit. The logic circuit determines the next microcode to be loaded by the field programmable gate array based on the logic according to the input internal status information and an external request signal, and outputs a next microaddress signal.

[0008] The decoder decodes the next micro address signal output from the logic circuit and selects the next micro code. The microcode storage means outputs the microcode selected by the decoder from the stored plurality of microcodes to the field programmable gate array. The field-programmable gate array changes the internal connection state by the microcode thus loaded, and forms a logic circuit determined by the microcode. In this configuration, since the field programmable gate array and the microcode storage means are connected in parallel, the overhead involved in transferring microcode from the microcode storage means to the field programmable gate array is much shorter.

[0009]

An embodiment of the present invention will be described below. FIG. 1 shows a block diagram of a semiconductor integrated circuit.

The semiconductor integrated circuit includes a package 1 containing a field programmable gate array (hereinafter referred to as an FPGA) 3, a field programmable gate array (hereinafter referred to as an FPGA) 5 as a logic circuit, a decoder 7, and a micro ROM 9. I have. This semiconductor integrated circuit includes two signal systems. One is FPGA3
I / O signal processing system with the main configuration, the other is FPGA
5, a control signal system mainly composed of a decoder 7 and a micro ROM 9. An input terminal 1 for inputting a signal to be processed by the FPGA 1 as an input / output signal processing system in the package 1
1, 12, 13, and 14, and output terminals 15, 16, 17, and 18 for outputting processed signals. Also,
The package 1 has, as a control signal system, input terminals 21, 22, 23, 24, 25, 26, 2 for request signals from the outside.
7, 28 are provided.

The FPGA 3 includes a logic block, an I / O block, internal connection elements, and a built-in memory. The function of the logic block, the function of the I / O block, and the connection of the internal connection elements are configurable, and an arbitrary logic circuit is formed based on the connection of the configuration program stored in the internal memory and the processing information. FPG
The signals to be processed in A3 are input terminals 11, 12, 13,
14 is input. The signals processed by the FPGA 3 are output from the output terminals 15, 16, 17, and 18.

The FPGA 5 forms a logic circuit for performing a predetermined process by combining an AND circuit and an OR circuit according to a configuration program stored in a built-in memory. The input terminals 21 to 21 are connected to the FPGA 5.
28, a request signal from the outside is input, and the above F
The internal status information 29 of the PGA 3 is input. FPG
The logic circuit formed in A5 is an FPGA 3 that matches internal status information of the FPGA 3 and a request signal from the outside.
Is a logic for calculating the next micro address.

The decoder 7 decodes the next micro address output from the FPGA 5 and selects a micro code constituting the configuration program stored in the micro ROM 9.

The micro ROM 9 is a ROM storing micro codes of a configuration program. The micro ROM 9 and the FPGA 3 are connected in parallel. For example, if the microcode is 100 bits per word, 100 outputs from the micro ROM 9 are FP
It has a configuration to input to GA3. This micro ROM 9
Outputs the microcode specified by the microaddress by the decoder 7 to the FPGA 3. In the embodiment, the FP
In order to rewrite the operation configuration of the GA 3 individually in the areas A, B, C, etc., the micro ROM 9 stores microcodes corresponding to the areas.

The semiconductor integrated circuit having the above configuration functions as follows. In the input / output signal system, the input terminals 11, 12,
Input signals input from 13 and 14 are operated by the logic circuit of the FPGA 3 and output from output terminals 15, 16, 17 and 18. The internal status information of FPGA3 is FP
Input to GA5.

In the control signal system, the FPGA 5 receives a request signal from the outside inputted from the input terminals 21 to 28 and the internal status information 29 from the FPGA 3,
The next status information of the FPGA 3, that is, the next operation configuration of the FPGA 3 is determined. Then, it outputs a next micro address signal indicating the next status information.

The decoder 7 decodes the next micro address signal output from the FPGA 5 and outputs it to the micro ROM 9. Thereby, the micro ROM 9 stores the micro code specified by the input micro address in the FPGA 3
Output to Since the micro ROM 9 and the FPGA 1 are connected in parallel, the transfer time of the micro code is extremely short. The FPGA 3 forms a logic circuit based on the loaded microcode.

A specific operation example will be described below. For example, it is assumed that a request signal from the outside requests the processing of the contents shown in the flowchart of FIG. The processing of FIG.
Is set to C (S100), and the value of C is determined (S110). If C is 0, the complement of D is set to C
(S120).

In this process, first, a wired logic circuit 41 (FIG. 3) for performing a process corresponding to S100 is formed in the FPGA 3 based on the microcode stored in the built-in memory. For this reason, the output of C is set to 1 when the outputs of A and B are both 1. FPG
The output of C is input to A5 as internal status information of the FPGA3. When the value of C becomes 0 as requested from the outside, the FPGA 5 performs the next operation configuration of the FPGA 3,
The next micro address signal indicating the wired logic circuit 43 (FIG. 4) performing the processing corresponding to 120 is output. The decoder 7 decodes the next micro address signal output from the FPGA 5 and outputs it to the micro ROM 9. As a result, the micro ROM 9 outputs the micro code specified by the input micro address to the FPGA 3. The FPGA 3 forms the wired logic circuit 43 by the microcode loaded in a very short time. Therefore, the overhead falls within a practical time, and the FPGA 3 is connected to the wired logic circuit 4.
3 outputs the complement of D as C.

As described above, according to the semiconductor integrated circuit of the embodiment, since the overhead is short, it is possible to execute a process with a conditional branch and to dynamically change the configuration.
This has the effect of realizing a versatile semiconductor integrated circuit that draws out the potential of PGA.

Further, in the embodiment, since the operation configuration of the FPGA 3 is changed for each divided area, only the necessary area can be rewritten, and there is an effect that the overhead is shortened. Further, unnecessary information such as providing the same connection information as before to an area where the connection is not changed may be reduced.

Although the embodiment has been described above, the present invention is not limited to the embodiment at all. For example, it goes without saying that the present invention can be implemented in various modes without departing from the spirit of the present invention. The physical configurations of the FPGA 3 and the FPGA 5 may be the same. Further, one FPGA may be divided into two regions to form the FPGA 3 and the FPGA 5. FP
The logic of the GA 5 may be programmed in advance, or may be rewritten by a configuration program stored in the micro ROM 9.

[0023]

As described above, according to the semiconductor integrated circuit of the present invention, the overhead of the FPGA is significantly reduced, and the dynamic configuration of the field programmable gate array can be changed in a very short time. Therefore, there is an excellent effect that a versatile semiconductor integrated circuit using an FPGA can be realized, for example, a process with conditional branching is also possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a flowchart illustrating an operation of the semiconductor integrated circuit;

FIG. 3 is an explanatory diagram of an operation of the semiconductor integrated circuit.

FIG. 4 is an explanatory diagram of an operation of the semiconductor integrated circuit.

FIG. 5 is a block diagram showing a usage example of a conventional FPGA.

[Explanation of symbols]

1 ... Package, 3 ... FPGA, 5 ... FPG
A, 7: Decoder, 9: Micro ROM

Claims (1)

(57) [Claims] 1. A field-programmable gate array for changing an internal connection state by a loaded microcode to form a logic circuit determined by the microcode, an internal status information of the field-programmable gate array, and an external request signal Is determined based on a predetermined logic in accordance with the internal status information and an external request signal, and a next micro address signal indicating the determined micro code to be loaded by the field programmable gate array. A decoder that decodes the next microaddress signal output from the logic circuit and selects the next microcode, stores a plurality of microcodes, and stores the microcode selected by the decoder in the file. Microcode storage means for outputting to the field programmable gate array, the field programmable gate array, the logic circuit, the decoder, and the microcode storage means being contained in one package, and the field programmable gate array And a microcode storage means connected in parallel.