JPH05298068A - Comparator - Google Patents

Abstract

PURPOSE:To provide the comparator to control output by two threshold values and to reduce the number of circuits. CONSTITUTION:At the comparator which outputs a compared result 110 as true when an input value 101 reaches the value equal to a first threshold value 102 and outputs the compared value 110 as false when the input value 101 reaches the value smaller than a second threshold value 103 after that, whether the input value 101 reaches the value equal to the first threshold 102 or not is judged by an equivalence comparator 1. After that, whether the input value 101 reaches the value smaller than the second threshold value 103 is judged by a large/small comparator 2, and the outputs of the equivalence comparator 1 and the large/small comparator 2 is stored by a storage means 3. By a comparison result output control means 8, the compared result 110 is outputted from output 104 of the equivalence comparator 1, output 107 of the large/small comparator 2, and output 105 of the storage means 3. The number of circuits can be reduced by performing the judgement of whether the input value 101 reaches the value smaller than the second threshold value 103 or not by the large/small comparator 2.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to comparators used to control the amount of data held in memory.

[0002]

2. Description of the Related Art Recently, it has been desired to simplify a circuit for setting an input signal value between two threshold values when performing data processing using a digital computer.

A conventional comparator will be described below with reference to the drawings. As shown in FIG. 3, the conventional comparator is
An equality comparator 21 that outputs 1 when the input value 201 and the first threshold 202 are equal is connected to the storage means 24 and the NOR circuit 25, and outputs a value obtained by subtracting 1 from the second threshold 203. The subtractor 22 that performs the operation is connected to the equality comparator 23. The equivalence comparator 23 receives the input value 201 and the subtraction result 204.
When the values are equal, 1 is output and the storage means 24 and the NOR circuit 26 are connected. Storage means 24 is NOR circuit 25
Connected to the NOR circuit 26 and outputs the comparison result 209. The comparison result output control means 27 outputs the output 205 of the equivalence comparator 21 and the output 207 of the equivalence comparator 23.
And the output 206 of the storage means 24, when the input value 201 reaches a value equal to or more than the first threshold value 202, the comparison result 209 is output as 1, and then the input value 20
The NOR circuit 25 outputs the comparison result as 0 when 1 reaches a value smaller than the second threshold value 203.
And a NOR circuit 26.

The storage means 24 outputs 1 after 1 clock when the terminal J becomes 1 and outputs 0 after 1 clock when the terminal K becomes 1.

The NOR circuits 25 and 26 output 1 when 0 is input to the two input terminals, and output 0 otherwise.

Regarding the comparator configured as described above,
The operation will be described below with reference to FIGS. 3 and 4. Here, the comparator shown in FIG. 3 outputs the comparison result 209 as 1 when the input value 201 reaches a value equal to the first threshold value 202. On the other hand, when the input value 201 is equal to or greater than the second threshold value 203, 1 is output,
If it is smaller, it is output as 0.

However, the above two threshold values are set such that the first threshold value 202 ≧ the second threshold value 203. The input value 201 indicates the output of a counter or the like, and is incremented or decremented by one.

First, as shown in the state A of FIG.
The operation when 01 reaches a value equal to the first threshold value 202 will be described.

When the input value 201 reaches a value equal to the first threshold value 202, the equivalence comparator 21 outputs the equivalence comparison result 205 as 1 as shown in FIG. 4 (e). NO
The R circuit 25 outputs the equivalence comparison result 205 as shown in FIG.
Becomes 1, the NOR result 208 is output as 0.
When the input value 201 reaches a value equal to the first threshold value 202, the equivalence comparator 23 outputs the equivalence comparison result 207 as 0 as shown in FIG.
6 outputs the comparison result 209 as 1 as shown in FIG.

Next, the operation after the input value 201 reaches a value equal to the first threshold value 202 as shown in the state B of FIG. 4 will be described.

In the storage means 24, the equivalence comparison result 205 is 1
After 1 clock, the stored value is 2 as shown in FIG.
06 is output as 1. At this time, the NOR circuit 25
Has a stored value 206 of 1, the NOR result 208 is output as 0 as shown in FIG. NOR circuit 26
, The NOR result 208 is 0, so the equivalence comparison result 2
Until 07 becomes 1, the comparison result 2 as shown in FIG.
09 is output as 1. The equivalence comparison result 207 becomes 1 when the input value 201 reaches a value smaller than the second threshold value 203.

From the above description, in the comparator shown in FIG. 3, the input value 201 is the first threshold value 2 as shown in FIG.
If the input value 201 reaches a value smaller than the second threshold value 203, the comparison result 20
It can be seen that 9 is output as 1.

Next, the operation when the input value 201 reaches a value smaller than the second threshold value 203 as shown in the state C of FIG. 4 will be described.

The subtractor 22 outputs a subtraction result 204 obtained by subtracting 1 from the second threshold value 203 to the equivalence comparator 23 as shown in FIG. The equivalence comparator 23 receives the subtraction result 204 obtained by subtracting 1 from the second threshold value 203 and the input value 201.
When the two are equal, as shown in FIG.
Is output as 1. That is, the equivalence comparison result 207 is
It becomes 1 when the input value 201 reaches a value smaller than the second threshold value 203. When the equivalence comparison result 207 becomes 1, the NOR circuit 26 outputs the comparison result 20 as shown in FIG.
9 is output as 0.

Next, the operation after the input value 201 reaches a value smaller than the second threshold value 203 as shown in the state D of FIG. 4 will be described.

In the storage means 24, the equivalence comparison result 207 is 1
After 1 clock, the stored value is 2 as shown in FIG.
06 is output as 0. In the NOR circuit 25, both the equivalence comparison result 205 and the stored value 206 become 0,
The NOR result 208 is output as 1 as shown in FIG. Since the NOR result 208 becomes 1, the NOR circuit 26 outputs the comparison result 209 as 0 as shown in FIG.

Therefore, the comparator shown in FIG. 3 outputs the comparison result 209 as 1 when the input value 201 reaches a value equal to the first threshold value 202. After that, 1 is output while the input value 201 is equal to or greater than the second threshold value 203, and when it reaches a value smaller than the second threshold value 203, the comparison result 209 is output as 0. To do.

Next, when the input value 201 is a value represented by 4 bits, the circuit amount necessary for realizing the comparator shown in FIG. 3 will be described.

As shown in FIG. 5, equivalence comparators 21 and 2 are provided.
In the circuit configuration of 3, if the four transistors form one gate, the equivalence comparator requires 15 gates, and the circuit configuration of the subtractor 22 shown in FIG. 6 requires 17 gates.

Therefore, in order to realize the comparator shown in FIG. 3, the equivalence comparator 21 15 gates subtractor 22 17 gates equivalence comparator 23 15 gates storage means 24 9 gates NOR circuit 25 1 gate NOR circuit 26 1 gate A total of 58 gates are required.

As described above, even with the conventional configuration, it is possible to realize a comparator in which the comparison result is controlled by two threshold values.

[0022]

However, in the above-mentioned conventional configuration, even when the input value 201 is a value represented by 4 bits, 58 gates are required to realize it, and the circuit amount becomes large. Had.

The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a comparator having a smaller circuit amount than the conventional comparator.

[0024]

In order to achieve the above object, the comparator of the present invention uses the outputs from the large and small comparators by providing a large and small comparator in place of the subtractor 22 and the equivalence comparator 23. It has a configuration for controlling the comparison result.

[0025]

According to the present invention, the circuit amount can be made smaller than that of the conventional comparator by using the magnitude subtractor in place of the conventional subtractor and the equal value comparator in the above-mentioned structure.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, in the comparator of the present embodiment, the equivalence comparator 1 that outputs 1 when the input value 101 is equal to the first threshold value 102 is stored in the storage means 3 and the OR circuit 4. The magnitude comparator 2 that is connected and outputs 1 when the input value 101 is the second threshold value 103 or more is
It is connected to the AND circuit 5. The storage unit 3 is connected to the OR circuit 4 and the NAND circuit 5, and the NAND circuit 5 is N
The inverting circuit 6 is connected to the OR circuit 7 and is connected to the storage means 3 and N.
Connected to the OR circuit 7, the comparison result 11 from the NOR circuit 7
0 is output. The comparison result output control means 8 determines that the input value 101 has reached the same value as the first threshold value 102 or more from the output 104 of the equality comparator 1, the output 107 of the magnitude comparator 2 and the output 105 of the storage means 3. Sometimes the comparison result 110
Is output as 1, and thereafter, when the input value 101 reaches a value smaller than the second threshold value 103, the comparison result 1
10 is output as 0, and the OR circuit 4 and NAND
It is composed of a circuit 5, an inverting circuit 6, and a NOR circuit 7.

The storage means 3 outputs 1 after 1 clock when the terminal J becomes 1 and outputs 0 after 1 clock when the terminal K becomes 1.

The OR circuit 4 outputs 0 when 0 is input to the two input terminals, and outputs 1 otherwise.

The NAND circuit 5 outputs 0 when 1 is input to the two input terminals, and outputs 1 otherwise.

The inverting circuit 6 outputs a value obtained by inverting the positive / negative of the input value. The NOR circuit 7 outputs 1 when 0 is input to the two input terminals, and outputs 0 otherwise.

Regarding the comparator configured as described above,
The operation will be described below with reference to FIGS. 1 and 2.

First, as shown in the state A of FIG.
The operation when 01 reaches a value equal to the first threshold value 102 will be described.

When the input value 101 reaches a value equal to the first threshold value 102, the equivalence comparator 1 outputs the equivalence comparison result 104 as 1, as shown in FIG. OR
In the circuit 4, since the equivalence comparison result 104 is 1, the circuit shown in FIG.
The OR result 106 is output as 1 as shown in (f). At this time, since the input value 101 is equal to or larger than the second threshold value 103, the magnitude comparator 2 outputs the magnitude comparison result 107 as 1 as shown in FIG. NAND circuit 5
Outputs 1 as the OR result 106 and the magnitude comparison result 107, the NAND result 109 is output as 0 as shown in FIG. Since the magnitude comparison result 107 is 1, the inverting circuit 6 outputs the inversion result 108 as 0 as shown in FIG. Therefore, the NOR circuit 7 outputs the inversion result 108.
Since both the NAND result 109 and 0 are 0,
The comparison result 110 is output as 1 as in (j).

Next, the operation after the input value 101 reaches the value equal to the first threshold value 102 as shown in the state B of FIG. 2 will be described.

The storage means 3 stores the stored value 105 as shown in FIG. 2E after one clock when the equivalence comparison result 104 becomes 1.
Is output as 1. The storage value 105 of the OR circuit 4 is 1
Therefore, the OR result 106 is output as 1 as shown in FIG. At this time, since the magnitude comparison result 107 of the NAND circuit 5 is 1, the NAND circuit 5 performs NAND as shown in FIG.
The result 109 is output as 0. Further, since the magnitude comparison result 107 is 1, the inverting circuit 6 outputs the inversion result 108 as 0 as shown in FIG. Therefore, NO
Since both the inversion result 108 and the NAND result 109 are 0 in the R circuit 7, as shown in FIG.
Output 0 as 1.

From the above description, it is understood that the comparator shown in FIG. 1 outputs the comparison result 110 as 1 when the input value 101 is equal to or larger than the first threshold value 102.

Next, the operation when the input value 101 reaches a value smaller than the second threshold value 103 as shown in the state C of FIG. 2 will be described.

When the input value 101 reaches a value smaller than the second threshold value 103, the magnitude comparator 2 outputs the magnitude comparison result 107 as 0 as shown in FIG. 2 (g). NAND
In the circuit 5, the magnitude comparison result 107 is 0, so that FIG.
The NAND result 109 is output as 1 as shown in (i). Since the NAND result 109 is 1, the NOR circuit 7 outputs the comparison result 110 as 0 as shown in FIG. At this time, since the magnitude comparison result 107 is 0, the inversion circuit 6 outputs the inversion result 108 as 1 as shown in FIG.

Next, the operation after the input value 101 reaches a value smaller than the second threshold value 103 as shown in the state D of FIG. 2 will be described.

The storage means 3 outputs the stored value 105 as 0 after one clock when the inversion result 108 becomes 1, as shown in FIG. At this time, the OR circuit 4 outputs the OR result 106 as 0, as shown in FIG. 2F, because the equivalence comparison result 104 and the stored value 105 are 0. Since the OR result 106 is 0, the NAND circuit 5 outputs the NAND result 109 as 1 as shown in FIG. Since the NAND result 109 is 1 in the NOR circuit 7, FIG.
The comparison result 110 is output as 0 as in (j).

From the above description, the comparator shown in FIG.
It can be seen that the comparison result 110 is output as 0 after the input value 101 reaches a value smaller than the second threshold value 103.

Therefore, the comparator shown in FIG. 1 outputs the comparison result 110 as 1 when the input value 101 reaches a value equal to the first threshold value 102. After that,
1 is output while the input value 101 is equal to or greater than the second threshold value 103, and the input value 101 is the second threshold value 1
When the value less than 03 is reached, the comparison result 110 is set to 0.
Output as.

Next, when the input value 101 is a value represented by 4 bits, the circuit amount necessary for realizing the comparator shown in FIG. 1 will be described.

As shown in the above-mentioned conventional example, the correspondence relationship between each combinational circuit and the number of gates is to realize the equivalence comparator shown in FIG. 5 if one gate is composed of four transistors. 15 gates are required, as shown in FIG.
The size comparator shown in (2) requires 22 gates to realize.

Therefore, in order to realize the comparator of FIG. 1, the equality comparator 1 15 gates magnitude comparator 2 22 gates storage means 3 9 gates OR circuit 4 and NAND circuit 5 2 gates inverting circuit 6 1 gate NOR circuit 7 1 gate A total of 50 gates are required.

As described above, according to the above-described embodiment, it is possible to reduce the circuit amount required for realizing the comparator in which the comparison result is controlled by the two threshold values.

For example, when the input value is a value represented by 4 bits, the circuit amount of 58 gates is conventionally required, whereas the circuit amount of 50 gates can be realized. That is, the circuit amount can be reduced by about 15%. The circuit amount that can be reduced increases as the number of bits of the input value increases.

In the above description, the case where the comparison result 110 from the comparison result output control means 8 is output as 1 may be displayed as true, and the case where the comparison result 110 is output as 0 may be displayed as false.

[0050]

As is apparent from the above embodiments, according to the present invention, it is possible to reduce the amount of circuits required to realize a comparator in which the comparison result is controlled by two threshold values. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a comparator according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the embodiment.

FIG. 3 is a block diagram of a conventional comparator.

FIG. 4 is an operation timing chart of the comparator.

FIG. 5 is a configuration circuit diagram of an equivalence comparator.

FIG. 6 is a configuration circuit diagram of a subtractor.

FIG. 7 is a circuit diagram of a size comparator.

[Explanation of symbols]

 1 Equivalence Comparator 2 Large / Small Comparator 3 Storage Means 8 Comparison Result Output Control Means 101 Input Value 102 First Threshold 103 Second Threshold 110 Comparison Results

Claims (1)

[Claims] 1. An equality comparator for controlling an output by two first and second threshold values and determining whether or not an input value has reached the same value as the first threshold value,
A magnitude comparator that determines whether or not the input value is equal to or greater than the second threshold value, a storage unit that stores that the input value has reached the first threshold value, and an output of the equal value comparator. From the output of the magnitude comparator and the output of the storage means, when the input value reaches the same value as the first threshold value,
Comparison result output control means arranged to output the comparison result as true and then output the comparison result as false when the input value reaches a value smaller than the second threshold value. Comparable comparator.