JPH06160453A - Method for evaluating phase comparator - Google Patents

Abstract

PURPOSE:To provide a method for evaluating phase comparators by which a phase comparator can be evaluated by extremely easily deciding the output state of the phase comparator in a DC sense without making any special circuit change. CONSTITUTION:After raising the terminal voltages (a) and (c) at two input terminals to high levels, the voltage (b) is returned to the high level after once lowering the voltage (b) to a low level and again returned to the high level after once more lowered to the low level, while the voltage (a) is fixed at the high level. When the voltage (b) is in a state A, the voltage reaches another state B (output is at the low level) from the state A through states C, I, and E. When the voltage (b) is in the state B, the voltage (b) returns to the state B through states E, B, and E. In case the voltage (b) is in the state I, the voltage (b) reaches the state B through the states E, B, and E.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an evaluation method for a phase comparator, and more particularly to an evaluation method for evaluating the electrical characteristics of the charge pump output of a charge pump type digital phase comparator used in a PLL circuit.

[0002]

2. Description of the Related Art Generally, in a charge pump type digital phase comparator used in a PLL circuit, its output has three output states of high level, low level and high impedance (Z). When shipping this PLL circuit as an IC, the basic characteristics are
It is necessary to measure the electrical characteristics of the charge pump output in one output state, for example, the DC drive capacity.

However, since this digital phase comparator is a sequential circuit, it is impossible to predict which of the three output states the output will be in when the power is turned on. Therefore, the electrical characteristics of the charge pump output are evaluated by using the following two evaluation methods. In the evaluation method, power on / off is repeated several times, and this is continued until three output states appear,
The electrical characteristics of the charge pump output in each output state were evaluated. In the evaluation method, a special terminal for setting the output state is provided, and the evaluation logic circuit is further incorporated to determine the output state, and the electrical characteristics of the charge pump output in each output state are evaluated.

[0004]

However, in the conventional evaluation method, since the power supply is repeatedly turned on / off until three output states appear, the measurement is redundant and time-consuming, and automatic measurement is performed. It had the drawback of being difficult. On the other hand, in the evaluation method, a dedicated terminal is newly provided and a circuit is newly added.
As the number of C terminals increases and the logic circuit becomes complicated,
There was a drawback that the number of components increased. Therefore, an object of the present invention is to provide an evaluation method of a phase comparator which can very easily determine the output state of the phase comparator in terms of direct current and evaluate the output state without special circuit modification. And

[0005]

In order to achieve the above object, in a method for evaluating a phase comparator according to the present invention, a charge pump type digital phase comparator having three output states of high level, low level and high impedance is provided. At
By controlling the logic levels of the terminal voltages of the two input terminals, one of the three output states is determined, and the electrical characteristic of the charge pump output in this determined output state is evaluated.

[0006]

In the charge pump type digital phase comparator, it is not possible to predict which of the three output states the output state will be when the power is turned on. Therefore,
First, one terminal voltage of the two input terminals is fixed to a high level (or low level), the other terminal voltage is set to a high level (or low level), and the logic level of the other terminal voltage is set to 2 By changing it more than once, the desired output state is determined. Furthermore, from this desired output state,
By controlling the logic level of the terminal voltage of one input terminal, the other two remaining output states are established.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an example of a digital phase comparator to which the evaluation method according to the present invention is applied. In FIG. 1, N11 to N14, N21 to N24,
N31 is a NAND gate having 2 to 4 inputs, and I _H ,
I _L is a current source which is on / off controlled by the outputs of the NAND gates N12 and N22, respectively. OUT is the output of this digital phase comparator. This digital phase comparator has an output state of high level (only I _H is on), low level (I _{L is} only on), and high impedance (depending on the phases of the input signals a and b of the two input terminals 1 and 2). The logic is configured so as to have three output states (I _H and I _L are both off).

In the digital phase comparator having such a structure, when the power is turned on and the terminal voltages a and b of the two input terminals 1 and 2 are both set to the high level, the output OUT is
In the state diagram of FIG. 2, any of the three output states can be achieved by being in the internal logic state of any of the state symbols A, B and I. That is, this phase comparator is a sequential circuit, and the output state is not determined only by the current input state of the input terminals 1 and 2, but the output state is determined based on the past state of the internal logic circuit. It

When the power is turned on, the output state is determined by the state of noise generated by the circuit element forming each gate. Therefore, when the power is turned on, the output state of the digital phase comparator is high level (H), low level (L),
It cannot be predicted which state of high impedance (Z) will occur. However, for example, after setting both the terminal voltages a and b of the input terminals 1 and 2 to the high level, the terminal voltage a of the input terminal 1 is fixed at the high level and the terminal voltage b of the input terminal 2 is once changed from the high level. It is assumed that the level is changed to a low level and then to a high level, and then to a low level and then to a high level.

If, at first, it is in state A,
According to the processing procedure described above, the state is A → C → I → E →
It changes to B and becomes the state B. If the state is initially B, the state is changed to B → E → B → E → B, and the state is changed to B. Furthermore, assuming that the state I was initially, I → E →
The state changes from B → E → B, and the state becomes the state B. That is, in any of the possible states A, B, and I, the output state is always the state B by changing the logic level of the terminal voltage b twice or more, and the output state is in the low level. The state can be determined, and the electrical characteristics of the charge pump output in that output state can be reliably evaluated.

Further, when trying to evaluate another state, since the current state is clear, it is possible to shift to any state. For example, in state B
If the terminal voltage a of the input terminal 1 is changed from a high level to a low level while the terminal potential b of the input terminal 2 is fixed, a state (state F) in which the output OUT is in a high impedance state can be determined. By changing the terminal voltage a of the high level to the low level, the state in which the output OUT is at the high level (state G) is determined, and the electrical characteristics of the charge pump output can be evaluated.

That is, to summarize the series of processing procedures described above, one terminal voltage a (or b) of the two input terminals 1 and 2 is fixed at a high level (or low level), and the other terminal voltage is fixed. b (or a) is high level (or low level)
Then, the desired output state is determined by changing the logic level of the other terminal voltage b (or a) twice or more. Further, by controlling the logic levels of the terminal voltages a and b of the two input terminals 1 and 2 from this desired output state, the other two output states are determined. According to this, the electrical characteristics of the charge pump output can be evaluated by determining the three output states of the digital phase comparator in a direct current manner without changing the circuit.

FIG. 3 is a block diagram showing another example of the digital phase comparator. In FIG. 3, N11 to N1
3, N21 to N23 are 2-input NAND gates, N31
Is a 4-input NAND gate, I1 and I2 are inverters, and I _H and I _L are current sources whose on / off is controlled by the outputs of the NAND gates N13 and N23. OUT
Is the output of this digital phase comparator. In this digital phase comparator, since some delay occurs when the circuit inputs a and b are inverted by the inverters I1 and I2, the circuit inputs a and b, the outputs a'and b'of the inverters I1 and I2, There is a timing relationship shown in the waveform diagram of FIG. 4 between the outputs a ″ and b ″ of the NAND gates N11 and N21.

The same processing procedure as in the above case can be applied to the digital phase comparator having the above structure. That is, for example, after the outputs a ″ and b ″ of the NAND gates N11 and N21 are both set to the high level, the output a ″ of the NAND gate N11 is fixed at the high level and the output b ″ of the NAND gate N21 is changed from the high level. It is assumed that the logic levels of the terminal voltages a and b of the two input terminals 1 and 2 are controlled so that the low level is once returned to the high level, and then the low level is again returned to the high level.

In the state diagram of FIG. 5, if the state is first in the state A, the state changes to A → D → I → C → B by the processing procedure described above, and becomes the state B. If the state B is initially, B → C → B → C →
It changes to B and becomes the state B. Further, if the state is initially state I, the state changes to I → C → B → C → B, and the state becomes state B. That is, regardless of the possible initial states A, B, and I, the output b ″ of the NAND gate N21 is changed twice or more by controlling the logic level of the terminal voltage b, so that the output is always output. The state becomes the state B, and the output state can be fixed to the low level state.
The electrical characteristics of the charge pump output in that output state can be reliably evaluated.

Further, when trying to evaluate another state, since the current state is clear, it is possible to shift to any state. For example, in state B
If the terminal voltage a is controlled to change the output a ″ of the NAND gate N11 from the high level to the low level and the high level while the output b ″ of the NAND gate N21 is fixed, the output OUT is in the high impedance state. (State I) can be determined, and by controlling the terminal voltage a so as to change the output a ″ of the NAND gate N11 to low level, the state in which the output OUT is high level (state E) is determined, and the charge pump The electrical characteristics of the output can be evaluated.

[0017]

As described above, according to the present invention,
In the charge pump type digital phase comparator which takes three output states, any one of the three output states is determined by controlling the logic level of the terminal voltage of the two input terminals. It is very easy to use the digital phase comparator 3 without changing the circuit.
It is possible to determine the three output states in terms of direct current and evaluate the electrical characteristics of the charge pump output.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a digital phase comparator.

FIG. 2 is a state diagram of the digital phase comparator of FIG.

FIG. 3 is a block diagram showing another example of a digital phase comparator.

FIG. 4 is a waveform diagram of an input unit in the digital phase comparator of FIG.

5 is a state diagram of the digital phase comparator of FIG.

[Explanation of symbols]

1,2 input terminal N11~N14, N21~24, N31 NAND gate I1, I2 inverter I _H, I _L current source

Claims (3)

[Claims] 1. A charge pump type digital phase comparator which has three output states of a high level, a low level and a high impedance. By controlling the logic levels of the terminal voltages of two input terminals, the three output states of the three output states are controlled. An evaluation method of a phase comparator, characterized in that any one of them is determined and the electrical characteristic of the charge pump output in the determined output state is evaluated. 2. The terminal voltage of one of the two input terminals is fixed to a high level (or low level), the other terminal voltage is set to a high level (or low level), and the other terminal voltage of 2. The phase comparator evaluation method according to claim 1, wherein the desired output state is determined by changing the logic level twice or more. 3. The other two output states are defined by controlling the logic levels of the terminal voltages of the two input terminals from the desired output state.
Evaluation method of the described phase comparator.