JPS63237284A - Magnetic bubble storage device - Google Patents

Abstract

PURPOSE:To decrease the power consumption as a control signal by providing a cascaded signal delay means, and a means inverting code of an input or an output and deriving AND with the other and obtaining a pulse shorter than the width of a clock pulse inputted to the delay means. CONSTITUTION:From a clock signal 100, the signals (a)-(d) of each different delay time are generated in the N pieces of delay elements 13 (13-1-13-N). A signal (e) is obtained by reading out successively all addresses of a PROM 12 as '1', and a signal (g) is obtained by the AND 19 of an output (b) of the delay element 13-1. Also, a signal (h) is obtained by the AND 20 of the signal (e) and the output (d) of the delay element 13-N. By setting an FF 22 by the signal (g), and resetting it by the signal (h), a control signal 117 is outputted. By the AND 21 of a signal (f) from an address 1 and the inverted 23 signal of the delayed signal (b) and the signal (c), a control signal 118 is generated. The pulse signal 118 is the minimum width required for the control of a magnetic bubble memory. According to such a constitution, the various kinds of signals having a time difference are generated, the device is operated by a control pulse signal having a small width by its combination, and the power consumption is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic bubble storage device, and particularly to a magnetic bubble storage device with a control signal generation circuit that consumes little power.

[Conventional technology]

Conventionally, magnetic bubble storage devices have been accompanied by a magnetic bubble memory control signal generation circuit used for data input/output.
This includes programmable read-only memory (
PROM) was used. This will be explained below using a specific example.

First, the magnetic bubble memory 1 is used in the magnetic bubble storage device, and this magnetic bubble memory is
A normal major line or major loop (hereinafter collectively referred to as major lines 6A and 6B), a minor loop 7, a magnetic bubble generator 2 that generates magnetic bubbles, and a write that moves the magnetic bubble from the major line 6A to the minor loop 7. A gate 3, a readout gate 4 for transferring from the minor loop 7 to the major line 6B, a reader 5 for reading out the magnetic bubbles, and a rotating magnetic field for moving the magnetic bubbles on the major lines 6A and 6B and on the minor loop 7. It is composed of an X coil 8 and a Y coil 9. The magnetic bubble memory 1 includes a magnetic bubble generator 2, a write gate 3, a read gate 4, and
A current pulse generating circuit 10 is included for causing current to flow through the coil 8 and the Y coil 9. (A configuration example is shown in Figure 7)
.

When recording data in the magnetic bubble memory, first, a magnetic bubble is generated in the bubble generator 2 by an input signal from the write input terminal 101. (This magnetic bubble corresponds to data "1°".

The case where no magnetic bubble is generated corresponds to data “0”). Next, when a rotating magnetic field controlled by the current pulse generation circuit 10 is applied to the entire magnetic bubble memory, the magnetic bubble moves on the measure line 6A. When the positional relationship between the magnetic bubble on the major line and the minor loop 7 matches, the magnetic bubble on the major line 6A is moved to the minor loop through the write gate 3, and data is recorded.

When reading data, the data to be read is moved to the read gate 4 using a rotating magnetic field. Next, the data on the minor loop 7 is transferred to the major line 6B through the read gate 4. The data on the major line is sequentially transferred to the reader 5 by a rotating magnetic field, and the data is read out and output from the output terminal.

FIG. 5 is a circuit diagram showing an example of the configuration of a conventional magnetic bubble storage device. A conventional magnetic bubble storage device has an address counter 11 and a programmable read-only
It is composed of a memory (hereinafter referred to as FROM) 12 and a magnetic bubble memory. When the clock signal 100 is input to the address counter 11, the address counter 11
The outputs Ao to A3 are constructed with shift registers and the like so that outputs as shown in FIGS. 6(a) to 6(d) can be obtained. Assuming that data "1" is written in addresses 1 to N of the PROM 12, the control signal 118 shown in FIG. 6(e) is output by sequentially reading the PROM 12 from address O. Also, in address 5 “
Assuming that 1'' has been written, Figure 6 (
A control signal 117 shown in f) is output. This is the control signal for the magnetic bubble memory. The signal shown in FIG. 6(f) is the minimum pulse width required to control the magnetic bubble memory. Since the minimum pulse width is about 100 nsec, the clock signal 100 needs to be about 10 MHz. Therefore, bipolar type electronic devices capable of high-speed operation have been used as electronic devices including PROMs.

[Problem that the invention seeks to solve]

The conventional magnetic bubble storage device described above generates a signal with a small pulse width that controls the magnetic bubble memory from a high-speed input clock, and because it includes a bipolar electronic device, it is capable of high-speed operation. Although it has advantages, it has the disadvantage of high power consumption.

Therefore, an object of the present invention is to provide a magnetic bubble memory with a control signal generating means that slows down an input clock, generates several types of signals with time differences using a delay element, and generates a signal with a small pulse width by combining the signals. It provides equipment.

[Means for solving problems]

The magnetic bubble storage device of the present invention comprises at least one cascaded signal delay means in the magnetic bubble storage device;
an inverting means for inverting one of the input signal and the output signal of the signal delaying means; and a signal of the other one of the input signal and the output signal of the signal delaying means passing through the inverting means. and a logical product means for obtaining a logical product with a signal, and the output of the logical product means that obtains a pulse signal shorter than the pulse width of the clock signal inputted to the delay means is configured as a control signal for the magnetic bubble memory.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

Fig. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, Fig. 2 is a diagram showing the operation of the first embodiment, and Fig. 3 shows the configuration of the second embodiment of the invention. The circuit diagram and FIG. 4 are diagrams showing the operation of the second embodiment.

As shown in FIG. 1, the first embodiment of the present invention includes a magnetic bubble memory 1, an address counter 11, a PROM 12,
It is composed of delay elements 13-1 to 13-N, AND circuits 19 to 21, a flip-flop 22, and inverter circuits 23 and 24. Note that, in general, the AND circuit 21 and the inverter circuit 23 are configured to correspond to the delay circuits 13-1 to 13-N.

First, from the clock signal 100 that is input, N delay elements 1B-1 to 13-N produce signals having different delay times (FIG. 2(a) to (d
)) occurs. This signal and the output signal of PROM12 (
The operations of the address counter 11 and the PROM 12 are the same as in the conventional example described above) are combined by a logic circuit to generate necessary signals. For example, FROM
Assuming that "1' has been written in addresses 0 to N-1 of and the output signal of the delay element 13-1 (Fig. 2 (
By performing a logical product of (b)) and (b)) using a single AND circuit, the signal shown in FIG. 2(g) is obtained in FIG. 1(g). Also, FIG. 1(e) shows the output signal of the PROM 12 (see FIG. 2(e)).
e))) and the output signal of the delay element 13-N (second
(d)) in the AND circuit 20, the signal shown in FIG. 2(h) is obtained in FIG. 1(h). By setting the flip-flop 22 with the output of the AND circuit 19 (FIG. 2(g)) and resetting the flip-flop with the output of the AND circuit 20 (FIG. 2(h)), A control signal 117 shown is output to the magnetic bubble memory 1.

Similarly, if "1" is written in address 1 of the PROM, the signal shown in FIG. 2(f) is obtained. When this signal is ANDed by the AND circuit 21 with the output of the delay element 13-0 (FIG. 2(b)) and the inverted signal of the output of the delay element 13-1 (FIG. 2(C)), Figure 2 (j)
A control signal 118 shown in is output to the magnetic bubble memory 1.

The minimum pulse width (approximately 100 nsec) of the pulse signal shown in Fig. 2 (j>) required to control the magnetic bubble memory
It is. Now, if 10 delay elements are used (equivalent to dividing 172 in FIG. 2(a) by 10), the clock signal 100 will be a signal of 500KH2. At this speed, even a C-MOS electronic device can operate. According to commercial product catalogs, the operating frequency of bipolar electronic devices (for example, PROM) is 25 MHz.
, power consumption is 500mW. On the other hand, C-MOS
The operating frequency of the electronic device is 4MH2, and the power consumption is 7
It is 5 mw.

Next, a second embodiment will be explained.

Referring to FIG. 3, the second embodiment of the present invention includes a magnetic bubble memory 1, address counters 11-0 to 11-N,
PROM41-0 to 41-N and delay elements 13-1 to 1
3-N, an inverter circuit 25, an AND circuit 26, and an OR circuit 27.

First, from the input clock signal 100, N delay elements 13-1 to 13-N produce signals having different delay times (FIG. 4(a)) as shown in FIGS. 3(a) to (d). ~(
d)) occurs. The address counters 11-0 to 11-N corresponding to this signal are operated, and the output of the PROM is sequentially read from address 0. 1st PROM41-
0 and address 1 of the second PROM41-1.
If the parameter has been written, the output is shown in Figure 3(e).
- At (f), the signals become as shown in Fig. 4 (e) and (f). When the output of FROM 41-1 is inverted by inverter circuit 25 and ANDed with the output of FROM 41-0, output 118 becomes as shown in FIG. 4(i). This is the minimum pulse width required to control the magnetic bubble memory.

Similarly, if "1'° has been written from address O to address N-1 of the third PROM 41-2 and from address 0 to address N of the N-th PROM 41-N, the FROM output will be as shown in FIG. (g) and (h) as shown in Figure 4 (g) and (h).This PR
By taking the logical sum of the output of the OM41-2 and the output of the PROM41-N, the output 17 becomes as shown in FIG. 4(J). Although this embodiment has the disadvantage of requiring a large number of PROMs, it has the advantage that the logical path for the FROM output is simple.

〔Effect of the invention〕

As described above, the magnetic bubble storage device of the present invention has the advantage that by configuring the control signal generation circuit with a C-MO3 electronic device, it is possible to realize lower power consumption of the magnetic bubble storage device. here! Although we have only explained two types of output signals, there are AND circuits, inverter circuits,
Various types of output signals can be obtained by freely combining other logic circuits and PROM data. Further, reducing the power consumption of the magnetic bubble storage device is very effective for systems such as artificial satellites that aim to reduce the power consumption of the entire system.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, Fig. 2 is a diagram showing the operation of the first embodiment, and Fig. 3 shows the configuration of the second embodiment of the invention. 4 is a diagram showing the operation of the second embodiment, FIG. 5 is a circuit diagram showing an example of the configuration of a conventional magnetic bubble storage device, and FIG. 6 is a diagram showing the structure of the magnetic bubble storage device of FIG. 5. FIG. 7 is an explanatory diagram of a magnetic bubble memory used in a magnetic bubble storage device. 1...Magnetic bubble memory, 11.41-O to 41-N
...Address counter, 12.11-0 to 11-N.
...PROM, 13-1 to 13-N...delay circuit. Agent Patent Attorney Susumu Uchihara・' Single 1 2nd W (L) 6------C
1) ←−−−−−−−−−
(I,

Claims (1)

[Claims] In a magnetic bubble storage device, at least one cascaded signal delay means, an inversion means for inverting one of an input signal and an output signal of the signal delay means, and an input signal of the signal delay means. and logical product means for calculating a logical product of the other one of the output signals and the signal passed through the inverting means, and a pulse signal shorter than the pulse width of the clock signal input to the delay means is obtained. A magnetic bubble storage device characterized in that the output of the logical product means is used as a control signal for the magnetic bubble memory.