JPH06333380A - Pointer - Google Patents

Abstract

PURPOSE:To prevent the retardation of the operating speed of a pointer due to the increase of a number of stages of shift registers caused by the increase of memory capacity and due to the increase of the load. CONSTITUTION:Registers 110-1, 110-2,... on each stage of a shift register 110 are reset by means of reset signals Ca, Cb and the output of the register 110-1 on a first stage becomes 'L'. When control signals Aa, Ab are inputted, the output 'L' of the register 110-1 on the first stage is shifted one bit at a time. Logical operation of the outputs on the respective stages of the register 110 and control signals B1-B4 performing dividing operation is executed in a gate group 120 and data buses DBa, DBb are successively connected to the respective stages of a register 200. Consequently, by performing the dividing operation of the control signals B1-B4, the load is reduced and pointer operation is performed at high speed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a FIFO (First In F
irst Out) A pointer using a shift register in a memory or the like.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a configuration example of a conventional pointer in a FIFO memory or the like. This pointer 1 is a data bus DB that is complementary to the registers 30 in multiple stages.
a and DBb are sequentially connected by a plurality of pairs of N-channel MOS transistors (hereinafter referred to as NMOSs) 31 and 32 to perform data writing and reading operations of the register 30. Pointer 1 is
The shift register 2 and a gate group 3 that gate-controls the output of the shift register 2 are included. The shift register 2 is composed of a plurality of stages of registers 10. The first-stage register 10 includes an NMOS 11a that resets the register 10 by a reset signal Ca, two-stage tri-state inverters 12 and 13 that are on / off controlled by complementary control signals Aa and Ab, and the tri-state inverter 12. , 13 to hold the outputs of the signal holding circuits 14 and 15. The register 10 in the second and subsequent stages has substantially the same circuit configuration as the register 10 in the first stage, but instead of the resetting NMOS 11a, a P-channel MOS transistor (hereinafter referred to as PMOS) which is turned on / off by an inverted reset signal Cb. ) 11b is only provided.

The gate group 3 has inverted output signals OZ ₁ , OZ.
It is composed of a plurality of two-input NOR gates 20 for outputting Z ₂ , .... The NOR gate 20 in each stage is a circuit that is controlled to open / close by a common control signal B and outputs the output of the register 10 in each stage in the form of inverted output signals OZ ₁ , OZ ₂ , .... Each stage of the register 30 has an inverted output signal OZ.
Plural pairs of Ns that are turned on and off by ₁ , OZ ₂ , ...
Complementary data bus DBa via MOS 31, 32
It is connected to DBb. Each stage of the register 30 is composed of two inverters 33a and 33b connected in anti-parallel. FIG. 3 is a timing chart of FIG. 2, and the operation of the pointer circuit of FIG. 2 will be described with reference to this figure.

First, the shift register 2 is reset by the complementary reset signals Ca and Cb, and the NMOS 11a in the first-stage register 10 is turned on. The PMOS 11b in the register 10 of each stage after the second stage is also turned on. When the NMOS 11a in the register 10 at the first stage is turned on, the output of the register 10 becomes "L" level. Next, complementary control signals Aa and A having waveforms as shown in FIG.
When b is input to the shift register 2, the output “L” level of the register 10 at the first stage is shifted to the register 10 at the subsequent stage bit by bit. The output of each stage of the shift register 2 and the control signal B are subjected to the NOR operation by the NOR gate 20 of each stage, and their inverted output signals OZ ₁ and OZ.
Z ₂ , ... Sequentially become “H” level. Then, the NMOSs 31 and 32 of the respective stages are sequentially turned on, and the data buses DBa and DBb and the signal holding circuits 33 in the register 30.
And are connected.

[0005]

However, in the conventional pointer, the number of stages of the shift register 2 increases as the memory capacity increases, and the signals Aa and A are accordingly increased.
The load increases due to an increase in the wiring length of b, B, and Cb and an increase in the number of stages of the NOR gate 20. This causes a problem that the high-speed operation of the pointer is hindered, which is difficult to solve. The present invention solves the problem of the above-mentioned conventional technique that the load of the signals Aa, Ab, and B increases as the memory capacity increases, and the load is reduced by the division operation of the control signal. , Provides a pointer that can operate at high speed.

[0006]

In order to solve the above-mentioned problems, the present invention provides a pointer such as a FIFO memory,
A shift register of k (however, k: any integer) stages that sequentially shifts a signal taken in by a first control signal input every n (however, n: any integer) cycle, and the shift register. Input the output signal of each stage of
K divided by n second control signals which are divided and input every n cycles to output and output the output signals
and n stages of gates.

[0007]

According to the present invention, since the pointer is configured as described above, the shift register sequentially shifts the signal taken in by the first control signal input every n cycles, and k.n stages. Supply to the gate. Each gate is
Gate control is performed based on the second control signal divided into n,
The output of each stage of the shift register is sequentially output. As a result, the second control signal division operation is performed, the load is reduced, and the pointer operation can be speeded up. Therefore, the above problem can be solved.

[0008]

1 is a circuit diagram of a pointer in a FIFO memory or the like showing an embodiment of the present invention. This pointer 1
00 is a data bus DBa complementary to the register 200,
DBb and DBb are sequentially connected to perform data writing and reading operations of the register 200, and k (where k is an arbitrary integer) stages of the shift register 1
10 and a gate group 120. The shift register 110 is reset by complementary reset signals Ca and Cb, and is controlled by complementary first control signals Aa and Ab. The k-stage registers 110-1, 110-2,
It consists of ... The first-stage register 110-1 is an NMOS 11 gate-controlled by a reset signal Ca.
1a, a tri-state inverter 112 which is on / off controlled by a control signal Ab, and a tri-state inverter 11 which is on / off controlled by a control signal Aa
3 and the signal holding circuits 114 and 115. The tri-state inverter 11 is connected to the ground potential VSS.
2 input terminals are connected and the output terminal is connected to the NMOS 1
It is connected to the ground potential VSS via the source / drain of 11a and is also connected to the input terminal of the tri-state inverter 113. Tri-state inverter 1
A signal holding circuit 114 is connected to the 12 output terminals. The signal holding circuit 114 includes two inverters 114.
This is a configuration in which a and 114b are connected in anti-parallel. Similarly,
To the output terminal of the tri-state inverter 113, the signal holding circuit 115 including the inverters 115a and 115b connected in anti-parallel is connected. The registers 110-2, ... In the second and subsequent stages are circuits similar to those of the register 110-1 in the first stage, but the reset NMOS 111a is used.
Instead, a reset PMOS 111b is provided only. PMOS 11 for reset
1b is gate-controlled by the reset signal Cb, and its source / drain is connected between the power supply potential VCC and the output terminal of the tri-state inverter 112.

The gate group 120 includes a second control signal B ₁ , which performs a division operation of n (where n is an arbitrary integer, for example, 4).
Two-input NOR gates 121-1 to 121-4, 122- of k · n stages, which are gate-controlled by B ₂ , B ₃ , and B ₄ .
1-122-4, ... 4-stage NOR gates 121-1～121-4 has one input terminal connected to an output terminal of the first-stage register 110-1, the other input terminal is the control signal _{B 4, B 3, B 2} , B Connected to ₁ respectively. Similarly, each stage NOR gate 122-
One of the input terminals of the registers 1 to 122-4, ...
0-2, ... Is connected to the output terminals, and the other input terminals are connected to the control signals B ₁ , B ₂ , B ₃ , and B ₄ , respectively. NOR gates 121-1 to 121-4, 12 in each stage
2-1 to 122-4, ... Inverted output signals OZ _{1 to} OZ
_8, ... is, a plurality of pairs of NMOS211-1,212-1~
The gates of 211-8, 212-8, ... Are respectively connected. Each NMOS 211-1, 212-1 to 211
Sources / drains of -8, 212-8, ... Are connected to complementary data buses DBa, DBb and input / output terminals of each stage of the register 200, respectively. Register 200
Is a plurality of stages of signal holding circuits 220-1 to 220-8, ...
It is composed of. Signal holding circuits 220-1 and 220-2 at each stage
20-8, ... are two inverters 2 connected in anti-parallel
20a and 220b, respectively.

FIG. 4 shows the control signals B ₁ , B ₂ , B of FIG.
₃ is a circuit diagram showing a configuration example of a control signal generation circuit that generates B ₃ and B ₄ . The control signal generation circuit divides the control signal B into n (for example, 4) and divides each of the control signals B ₁ , B ₂ , and B.
_This is a circuit that operates ₃ and B ₄ every 4 cycles. This control signal generation circuit is reset by a reset signal RSRAMD and complementary signals RCO and RCOZ to RC.
4, unit circuit 300-1 to 3 for outputting RC3Z
00-4 and the output signals RCO, RC1, RCOZ, R
Control signals BS ₁ , BS ₂ , BS ₃ and BS ₄ are obtained by obtaining the NOR of C1, RCO, RC1Z, RCOZ and RC1Z.
Of four 2-input NOR gates 331 to 334 for outputting The unit circuit 300-1 at the first stage is reset based on the signal obtained by inverting the reset signal RSRAMD by the inverter 301, and a complementary signal RCIN.
C, RCINCZ based complementary signals RCO, RCO
It is a circuit that outputs Z, and is a 2-input NOR gate 311
314, 2-input NAND gates 312, 318, 32
3. Inverters 313, 317, 324 for signal inversion
325, 326, PMOS 31 for analog switch
5, 320, 322, 327, and NMOS 316, 319, 321, 328 for analog switches.

Signal RCINCZ and NAND gate 323
Is connected to the input terminals of the NOR gate 311 and the NAND gate 312, respectively, the output signal of the NAND gate 312 is inverted by the inverter 313, and the output signal of the inverter 313 and the output signal of the NOR gate 311 are It is connected to the input terminal of the NOR gate 314. The output signal of the NOR gate 314 is the PMOS 3
15 and an analog switch made up of an NMOS 316 and inverted by an inverter 317.
Of the output signal of the NAND gate 323 through the analog switch composed of the NMOS 321 and the PMOS 322.
Connected to one of the input terminals. Inverter 317
Output signal of the inverter 301 and the output signal of the inverter 301 are
The output signal of the NAND gate 318 is connected to the input terminal of the D gate 318,
It is connected to the input terminal of the inverter 317 via an analog switch consisting of 20.

The output signal of the inverter 301 is a NAND
The NAND is connected to the other input terminal of the gate 323.
The output signal of the gate 323 is the inverters 324 and 326.
The signal RCOZ is inverted and output by the inverter 325, and the signal RCO is output by being inverted by the inverter 325. The output signal of the inverter 324 is a PMOS
It is connected to one input terminal of the NAND gate 323 through an analog switch composed of 327 and NMOS 328. PMOS 315, 327 and NMOS 31
9, 321 are gate-controlled by the signal RCINC, respectively. NMOS 316, 328 and PMOS 320, 3
22 is adapted to be gated by the signal RCINCZ. Other unit circuits 300-2 to 300-4
Also has substantially the same circuit configuration as that of the unit circuit 300-1 of the first stage, except that the input terminals of the NOR gate 311 and the NAND gate 312 have a two-input NAND gate 302 for obtaining the NAND of the output signals of the unit circuits of the preceding stages, It differs from the initial stage unit circuit 300-1 only in that an inverter 303 for inverting the output signal of the NAND gate 302 is added.

FIG. 5 is a timing chart of the control signal generation circuit shown in FIG. 4, and FIG. 6 is a timing chart of the whole of FIG. 1, and the circuit operation of FIGS. 1 and 4 will be described with reference to these. First, in the control signal generation circuit of FIG.
When the reset signal RSRAMD becomes "L" level, it is inverted by the inverter 301 and each unit circuit 300-
NAND gates 318 and 323 in 1 to 300-4 are opened. When the complementary clock signals RCINC and RCINCZ are input, the NMOS 31 is turned on when it is at the “H” level.
6, 321, 328 and PMOS 315, 320, 32
2, 327 complementarily turn on and off, and complementary signals RCO and RC having a cycle twice that of the clock signal RCINC.
OZ is output from the unit circuit 300-1 in the first stage. The unit circuits 300-2 to 300-4 of the second to fourth stages receive the output signal of the preceding stage and are four times the clock signal RCINC,
Complementary output signals RC1, of frequencies 8 and 16
It outputs RC1Z, RC2, RC2Z, RC3, RC3Z, respectively. These complementary output signals RCO, RC
OZ to RC3 and RC3Z are NOR gates 331 to 33.
The logical product is taken at 4 and the control signals BS _{1 to} BS ₄ are output. These control signals BS _{1 to} BS ₄ are inverted by a circuit (not shown) and supplied to the gate group 120 in the pointer 100 of FIG. 1 in the form of control signals B _{1 to} B ₄ .

In FIG. 1, the reset signal RSR of FIG.
Complementary reset signal Ca at the same timing as AMD,
Cb becomes "H" and "L" level, and shift register 1
The NMOS 111a and the PMOS 111b in the registers 110-1, 110-2, ... Of each stage in 10 are turned on and reset. Then, the output signal of the first-stage register 110-1 in the register 110 becomes "L" level.

Next, the complementary control signals Aa and Ab shown in FIG.
Is input to the shift register 110, the “L” level output signal of the register 110-1 at the first stage in the shift register 110 is shifted bit by bit. The output signal of each stage of the shift register 110 and the control signals B _{1 to} B _1
4 , the gate group 120 performs a NOR operation, the inverted output signals OZ _{1 to} OZ ₈ , ... Of which become “H” level in sequence, and the NMOS 211-1, 212-1 to 211-8,
212-8, ... sequentially turn on. Then, the complementary data buses DBa and DBb are sequentially connected to the signal holding circuits 220-1 to 220-8, ... Of each stage in the register 200, and the respective signal holding circuits 220-1 to 220-.
Data is written to or read from 8, ... As described above, in the present embodiment, the conventional control signal B is divided into _four to generate _four control signals B _{1 to} B ₄ , which are set to the “L” level once every four cycles (4 (Dividing operation), the load of the gate group 120 attached to each signal wiring of the control signals B _{1 to} B ₄ can be reduced to 1/4. In addition, the shift register 110
Can be reduced to 1/4, and the gate loads of the control signals Aa and Ab can be reduced to 1/4. Due to these load reduction effects,
High-speed operation of the pointer 100 is possible.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications. (A) The shift register 110 of FIG. 1 may have another circuit configuration. In addition, the gate group 120 may be configured by other gates such as a NAND gate. (B) The control signal generation circuit of FIG. 4 may have another circuit configuration. For example, the control signal B ₁ of the original, by shifting the control signal B ₁ bit by bit by using the shift register B
It is also possible to adopt a configuration in which ₂ , B ₃ , and B ₄ are sequentially output. Alternatively, the circuit configuration is not limited to the above-mentioned counter, and may be generated by using outputs of various counters. (C) Although the control signals B _{1 to} B ₄ are divided into four, they may be divided into arbitrary n divisions. In the case of the n-division configuration, the load is also 1 / n, and the pointer 100 can be made faster.

[0017]

As described in detail above, according to the present invention, a k-stage shift register for shifting the signal taken in by the first control signal input every n cycles, and the shift register. Input the output signal of each stage of
Since there are k · n stages of gates gate-controlled by n second control signals input every n cycles divided into n, the load of the second control signal is reduced to 1 / n. It is possible to reduce the number of stages in the shift register.
/ N, and the gate load of the first control signal can be reduced to 1/4. These load reducing effects enable high-speed operation of the pointer.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a pointer showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional pointer.

FIG. 3 is a timing chart of FIG.

FIG. 4 is a circuit diagram of a control signal generation circuit supplied to the pointer of FIG.

FIG. 5 is a timing chart of FIG.

FIG. 6 is a timing chart of FIG.

[Explanation of symbols]

100
Pointer 110
Shift register 110-1, 110-2
Register 120
Gate group 121-1 to 121-4, 122-1 to 122-4
NOR gate 200
Registers 211-1, 122-1 to 211-8, 212-8
NMOS 220-1 to 220-8
Signal holding circuit Aa, Ab
First control signal B _{1 to} B ₄
Second control signal Ca, Cb
Reset signal DBa, DBb
Data bus

Claims (1)

[Claims] 1. A shift register of k (however, k: arbitrary integer) stages which sequentially shifts a signal taken in by a first control signal inputted every n (however, n: arbitrary integer) cycles. And a gate of n · n stages which receives the output signals of the respective stages of the shift register, and is opened / closed by n second control signals which are divided into n and inputted every n cycles. A pointer characterized by having and.