JPS63245020A - Decoder circuit - Google Patents

Abstract

PURPOSE:To attain stable read/write of data by generating a noninverting signal of an input signal by an AND between the input signal and an inverter gate signal of the 2nd stage in the 3 stages of the inverter gates and an inverting signal by AND between the inverter gate signal of the 1st stage and the inverter gate signal of the 3rd stage respectively. CONSTITUTION:The noninverting signal is generated by an AND between an input signal and the inverter signal of the 2nd stage in 3 stages of inverter gates 3-5, 8-10 connected in series to cause the delay of gate and the inverting signal is generated by an AND between an inverter gate signal of the 1st stage and the inverter signal of the 3rd stage in 3 stages of the inverter gates 3-5, 8-10. Thus, the inverting signal and the noninverting signal do not simultaneously go to H at the fall of the input signal and the two decode signals are not simultaneously selected. Thus, the address of the memory cell is designated accurately and the data write/read is applied stably.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a decoder circuit used in a memory address decoder or the like.

2. Description of the Related Art Conventionally, this type of decoder circuit has had a configuration as shown in FIG. In FIG. 3, when an input signal A is applied to the input terminal 1, which is shown in FIG. is generated. Similarly,
When an input signal B is applied to the input terminal 2, an inverted signal B is generated at the inverter gate 23, and a non-inverted signal B is generated at the inverter gate 24.

By combining these generated signals A, A, B, and B, the logical product of A and B is taken by the AND gate 13, and a decoded signal shown in FIG. s4 is outputted to the output terminal 17. Similarly, the AND gate 14 takes the AND of A and B, and a decode signal is output to the output terminal 18. The AND gate 15 takes the AND of A and B, and the decode signal is output to the output terminal 19. , B is AND gate 1
6, and a decoded signal is output to the output terminal 2o.

In this way, decoded signals 0, 1.2.3 can be obtained from the combination of input signals A and B.

Although the above description has been made regarding a two-man power four-output decoder circuit, the same applies to an n-input, 2n-output decoder circuit.

Problems to be Solved by the Invention However, in such a conventional configuration, when the input signal falls, the rise of the inverted signal is earlier than the fall of the non-inverted signal by one gate delay time τ. When a combination of these signals is input to an AND gate, the decode signal that changes from "H" to "L" and the decode signal that changes from "L" to "H" in each AND gate output are delayed. Both become II Hj for a time τ, and two decode signals are selected at the same time.This means that, for example, in a memory address decoder circuit, two word line selectors or pit line selectors are selected at the same time. However, there was a problem in that the data written in the memory cells would be rewritten.

The present invention is intended to solve these problems, and aims to provide a decoder circuit that prevents two decode signals from being selected at the same time and allows data to be stably read and written to memory cells. It is something.

Means for Solving the Problem In order to solve this problem, the present invention provides an input signal and
To generate a gate delay, a non-inverted signal of the input signal is generated by ANDing the inverter signals of the second stage of the three stages of inverter gates connected in series, and the inverter signal of the first stage of the inverter gates is The inverted signal of the input signal is generated by ANDing the signal and the third stage inverter gate signal.

Function: With this configuration, it is possible to prevent the inverted signal and the non-inverted signal from going to "H" at the same time at the falling edge of the input signal, and to create a decoding circuit in which two decoded signals are not selected at the same time. All can be achieved.

Embodiment FIG. 1 is a logical configuration diagram of a decoder circuit according to an embodiment of the present invention. In FIG. 1, an input signal A, which is shown in FIG. When the voltage is applied, an inverted signal A is generated at the inverter gate 3 with a delay of 1 gate delay time τ, and an inverted signal A is generated at the inverter gate 4 with a delay of 2τ.
A non-inverted signal A is generated at 3τ, and an inverted signal A is generated at the inverter gate 6. AN
The fall of the non-inverted signal A of the D gate 6 is delayed from the fall of the input signal A, and its rise is delayed by 3τ from the rise of the input signal A.

Also, by ANDing the inverted signal A of the inverter gate 3 delayed by τ from the input signal A and the inverted signal A of the inverter gate 5 delayed by 3τ, the rise of the non-inverted signal A of the AND gate 7 is There is a delay of 4 times from the fall of the input signal A, and the fall is delayed by 2τ from the rise of the input signal A.

Therefore, the rise of the non-inverted signal A of the AND gate 6 is delayed by τ than the fall of the inverted signal A of the AND gate 7, and the rise of the inverted signal A of the AND gate 7 is delayed by τ. It is later than the falling edge of A by 3τ.

Similarly, when input signal B is applied to input terminal 2, AN
The rise of the non-inverted signal B of the D gate 11 is delayed by τ than the fall of the inverted signal B of the AND gate 12, and the rise of the inverted signal B of the AND gate 12 is as follows.
3 than the falling edge of the non-inverted signal B of the AND gate 11
It is delayed by τ.

By combining these generated signals A, A, B, and B, the logical product of A and B is taken by the AND gate 13, and the decode signal rOJ shown in FIG. 2 is output to the output terminal 17. is ANDed by AND gate 14,
A decode signal "1" is output to the output terminal 18, and A, H
The AND gate 16 outputs the decode signal "2" to the output terminal 19, and the AND of A and B is ANDed.
It is taken by the gate 16 and the decoded signal "3" is sent to the output terminal 20.
is output.

These decoded signals 0, 1, 2, and 3 are the signals A and A in which the rise of the inverted signal and the non-inverted signal is slower than the fall of the signal by τ or 3τ, as described above.

Since it is generated by taking the logical product of B and B, the rise of each decode signal is always τ or 3τ later than the fall, and the two decode signals become H” at the same time, that is, they are selected. will disappear.

This means that the word line selector or bit line selector can be prevented from being selected simultaneously in the address decoder circuit of the memory, and the data written in the memory cells can be stably held.

Although the above description has been made regarding a two-manpower four-output decoder circuit, the same applies to an n-input, 2n-output decoder circuit.

Effects of the Invention As described above, according to the present invention, it is possible to prevent an inverted signal and a non-inverted signal of an input signal from becoming the same signal at the same time, so it is possible to prevent two decoded signals from being selected at the same time. When used as a memory address decoder, it is possible to accurately address memory cells and to stably read and write data.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram showing a decoder circuit in an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit in FIG. 1, and FIG. 3 is a logic circuit diagram showing a conventional decoder circuit. FIG. 4 is a signal waveform diagram of each part of the circuit of FIG. 3. 1...Input terminal, 2...Input terminal, 3
~6,8~10...inverter game),6,1
1...AND gate (input non-inverted), 7.12
...AND gate (input inversion). 13-16・
...AND gate, 17...Output terminal,
18...Output terminal, 19...Output terminal, 2o...Output terminal. Name of agent: Patent attorney Tsuguo Nakao and 1 other person 3~
5. δ~ρ--4 inverter gate C・'f=ANDday) (input 1?, Urikosha) ttVt
o-injak3- Figure 3, 2-m- Avoid human power

Claims (1)

[Claims] Equipped with three stages of inverter gates connected in series to generate gate delay operation, and generates a non-inverted signal of the input signal by ANDing the inverter gate signal of the second stage of the three stages of inverter gates and the input signal. , and generates an inverted signal of the input signal by ANDing the inverter gate signal of the first stage and the inverter gate signal of the third stage of the three stages of inverter gates. .