JPS62180589A - Memory circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for transferring data frequently by transferring the data of a line shown by the line address information at one transfer cycle continuously from the position shown by the column address information at every column. CONSTITUTION:A line address signal 104 and a column address signal 105 are respectively supplied to a line decoder 2 and a column decoder 3, and when a data transferring signal 106 is active,the data by one line in a memory array 4 are selected by the line decoder 2. For the line address signal 104, through a line address latch circuit 9 and a line address counting-up circuit 10, 1 is integrated, given to the line decoder 2 as a new line address signal and the data for the next line are selected. For the data by one line respectively transferred to transferring gates 5 and 7, only the necessary number of the bit is shifted by data shifting circuits 11 and 12 in accordance with the column address signal 105. The AND is obtained by a data synthesizing circuit 13, the data by two lines come to be the data by one line and outputted to a data register 14.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to data transfer in a memory circuit.

(Prior Art) Conventionally, this type of memory circuit can transfer one row of data in one transfer cycle.

At this time, the data for one row to be transferred is the data of the row indicated by the row address information, and this data is transferred from the position indicated by the column address information. However, the transferred data could not span different lines.

(Problems to be addressed by the invention) In the conventional storage circuit described above, one transfer cycle
You can transfer rows of data. At that time, the data in the row indicated by the row address information is transferred from the position indicated by the column address information, but because the transferred data could not wrap around the row, depending on the value indicated by the column address information, the necessary The disadvantage is that it is necessary to transfer data frequently in order to obtain data.

An object of the present invention is to eliminate the above-mentioned drawbacks by continuously transferring the data of the row indicated by the row address information one row at a time from the position indicated by the column address information in one transfer cycle. The object of the present invention is to provide a complete storage circuit configured so that no data transfer is required.

(Means for determining the problem) A memory circuit according to the present invention includes an address input buffer, a row decoder and a column decoder, a memory cell array, a pair of transfer gates, a pair of data shift circuits,
It is configured to include a data synthesis circuit, a data register, a row address latch circuit, and a row address count-up circuit.

The address input buffer is for receiving and storing address information provided by a microprocessor or other device.

A row decoder and a column decoder are connected to the address input buffer and are for decoding address information.

The memory cell array is connected to row decoders and column decoders for storing data.

The transfer gate -i is for temporarily storing data in the memory cell array.

The pair of data shift circuits are companion circuits that shift data from the pair of transfer gates.

The data synthesis circuit 10 is for synthesizing data from a pair of data shift circuits.

The data register is for outputting the composite data.

The row address latch circuit is for latching address information in the address input buffer.

The row address count up circuit is for counting up the address information latched by the row address latch circuit.

(Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a memory circuit according to the present invention, and FIG. 2 is a waveform diagram showing signal waveforms of the memory circuit shown in FIG. 1. In FIG. 1, 1 is an address input buffer, 2 is a row decoder, 3 is a column decoder, 4 is a memory cell array, 5.7 is a first and second transfer gate, respectively, 9 is a row address latch circuit, and IO is a row An address count up circuit, 11 and 12 are first and second data shift circuits, 13 is a data synthesis circuit, and 14 is a data register.

In FIG. 1, the signal on signal line 1 (signal on Jl is an address signal given from an external microprocessor or other device; signal on signal line) 02 is an externally generated t-row address strobe signal. , Figure 2 (a
) has the signal waveform shown in The signal on signal line 103 is an externally generated column address strobe signal and has the signal waveform shown in FIG. 2(b).

Address input buffer 1 is an input buffer that amplifies the address signal on signal line 101.

The address signal on signal line 101 is internally taken in at the falling edge of the row address strobe signal on signal line 102, and the state at this time becomes the row address signal on line 104. The address signal on signal line 101 is
The column address strobe signal on the Ig line 105 is internalized at the falling edge of the column address strobe signal, and the state at this time becomes the column address signal on the Ig line 105. The row address signal on line 104 and the column address signal on signal line 105 are respectively decoded by row decoder 2 and column decoder 3, whereby one bit inside memory cell array 2 is normally selected. .

At this time, if the data transfer signal on the signal line 106 is active, the data for one row inside the memory cell array 2 selected by the row decoder 3 is transferred to the first and second transfer gates. will be forwarded to. Figure 2 (
C) shows the waveform of the data transfer signal on the signal line 106. The row address signal on signal line 104 is transferred to signal line 106.
The row address latch circuit 9 latches the address by the falling edge of the above data transfer signal. Here, the latched row address information is incremented by 1 to the current row address signal by the row address count up circuit 10 at the falling edge of the next signal on the signal dluZ, and is sent to the row decoder 3 as a new row address signal. Given. At this time, the one inside the memory cell array 2 selected by the row decoder 3
Data for one row, ie, data for one row following the first selected row, is selected. The selected row of data is also transferred to the first and second transfer gates 5 in the same manner as above.
．． Transferred to 7.

Each row of data transferred in this way is
According to the column address signal on the signal line 105, the data is shifted by the required number of pits inside the first and second data shift circuits II and 12. In the data shift circuit 11, the number indicated by the column address signal is subtracted from the number of bits for one row, and the data is shifted to the left by nine. Data shift circuit 12
Then, the column address signal is shifted to the right by the number indicated by the column address signal. In the data synthesis circuit 13, the outputs of the first and second data shift circuits 11 and 12 are ANDed, and two rows of data are output to the p1 data register 14 as one row of data. The data for one row inside the data register 14 obtained here corresponds to one continuous row on the memory cell array 4 indicated by the row address signal on the signal line 104 and the column address signal on the signal line 105. is equivalent to the data of

The data register 4 is composed of 4N data by a shift register, and is shifted one bit at a time by a shift clock input to a signal line 107 from the outside and outputted to the outside.

In the manner described above, exactly one row of data can be obtained from any address on the memory cell array 4 in one transfer cycle.

(Effects of the Invention) As explained above, the present invention can transfer the data of the row indicated by the row address signal one row at a time starting from the signal indicated by the column address signal in one transfer cycle. Regardless of the value indicated by the signal, it is sufficient to periodically provide a transfer cycle with a large period, so there is an effect that the transfer cycle does not have to be repeated as frequently as in the conventional method.

Therefore, the transfer cycle can be repeated periodically over a large period, and the external hardware for controlling the transfer cycle can be simplified.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a memory circuit according to the present invention. FIG. 2 is a waveform diagram showing an example of signal waveforms of the memory circuit shown in FIG. 1. 1...Address input buffer 2.3...Decoder 4...Memory cell array 5.7...Transfer gate 9...Row address latch circuit 10...Row address count up circuit 11, 12
...Data shift circuit 13...Data synthesis circuit 14...-Data registers 101 to 107...Signal line

Claims (1)

[Claims] an address input buffer for accepting and storing address information provided by a microprocessor or other device; a row decoder and a column decoder connected to the address input buffer for decoding the address information; and the row decoder. and a memory cell array connected to the column decoder for storing data;
a pair of transfer gates for temporarily storing data in the memory cell array; a pair of data shift circuits for shifting data from the pair of transfer gates; and a pair of data shift circuits for synthesizing the data of the pair of data shift circuits. a data synthesis circuit, a data register for outputting the synthesized data, a row address latch circuit for latching address information of the address input buffer, and the address information latched by the row address latch circuit. A memory circuit comprising: a row address count-up circuit for counting up.