JPS6252654A - Memory device - Google Patents

Abstract

PURPOSE:To expand memory capacity by utilizing an address space corresponding to the difference between the memory capacity and the capacity of an I/O device so as to additionally install an I/O space memory where an I/O read/write command is possible. CONSTITUTION:The memory 3, the I/O device 4 and an I/O space using memory 11 know that they are selected when addresses available from decoding the data of an address bus 1 are equal and when a memory read/write signal or the I/O read/write signal is received. The data in the memory 3, I/O device 4 and I/O space using memory 11 is outputted to the data bus 2 when the read signal is received. On the other hand, when the write signal is received, the data of the data bus 2 is inputted to the memory 3, the I/O device 4 and the I/O space using memory 11. At this time, the I/O device 4 and the I/O space using memory 11 decode the address from the address bus 1, and the difference between said addresses is used for the device 4 and the memory 11 to know whether they are selected or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device that uses I/O read/write signals as memory command signals.

[Conventional technology]

FIG. 2 shows, for example, a conventional memory device shown in 1APXa6 Family User's Manual Intel Japan KK, 1981, in which (1) is an address bus, (2) is a data bus, and (8) is a data bus. ) is memory, (4
) is an I/O device, (5) is a memory read/2 write signal that selects memory (8) for writing or reading, and (6) is a memory read/write signal that selects r/O device (4) and writes or reads. This is an I/O read/write signal. Note that the memory (8) and the I/O device (4) exchange data with a CPU (not shown) via an address bus α) and a data bus (S)t-.

Next, the operation will be explained.

The memory (8) or I/O device (4) has a matching address obtained by decoding the data on the address bus (1), and a memory read/write signal or an X/O read/write signal. Each person knows that they have been selected when they receive the . In the case of a read signal, the memory (8) or r/.

The data of the device (4) is output to the data bus (!l), and in the case of a write signal, the data of the data bus (2) is input to the memory (8) or the I/O device (4).

[Problem that the invention seeks to solve]

Since the conventional mesori device is configured as described above,
For writing to and reading from memory (8), only memory read/write signals can be used, r/.

Even if the capacity is p less than the memory capacity (actually, it is quite a bundle), the I/O area will not be used by the capacity difference between the number of memory capacities and the number of I/O capacities, and the address space will become meaningless. There were problems such as the existence of

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a memory device that can substantially expand the memory capacity by increasing the memory address space.

[Means for solving problems]

Memory device i according to this invention I/O device
The configuration is such that O space memories are arranged in parallel and these X/O space utilization memories respond to memory read/write signals of the same address.

[Effect]

The I/O weighted memory in this invention has a specific I/O
By using the O read/write signal.

It works to effectively utilize address space and increase memory capacity.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (11) is an I/O weight-based memory, which is installed in parallel with the I/O device (4), and which is
lo f HSS (4) is connected to respond to a different command signal with the same address, rlo IJ
- Dry drive signal (6) is connected to r/O device (4) or
/O space usage memory (select the cape).

Note that other components that are the same as those shown in FIG. 2 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

Next, the operation will be explained.

Memory (8) or I/O device (4) and I
A space usage memory (u) h, address bus (1) top t
When the addresses obtained by decoding the D f -data match and a memory read/write signal or an X/O read/write signal is received, each device knows that it has been selected. Then, in the case of a read signal, the data of the memory (8), I/O device (4), and I/O weight-based memory (11) is output to the data bus (2), and in the case of a write signal, , input the data on the data bus (2) to these.

In this case, the I/O device (4) and r/O weighted memory (11) decode the address from the U address bus (1), and depending on the difference in address, each determines whether or not it has been selected. Judge and confirm.

Note that in the above embodiment, the I/O device (4) and r/.

Although the same address is used as in the space usage memo IJ (11), in reality, even if the used areas at the same address are different and different command signals are used, the result is the same as in the above embodiment. be effective.

〔Effect of the invention〕

As described above, according to the present invention, memory capacity and I/O
The configuration uses the address space corresponding to the difference in device capacity to expand r/O weight-based memory that can perform r/O read/write commands, significantly increasing the usable memory capacity. This has the effect of providing something that can be expanded to.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram of a memory device according to an embodiment of the present invention, and FIG. 2 is a block connection diagram of a conventional memory device. (1) is the address bus, (8) is the memory, (4) is the I/
O device (1 is X/O space utilization memory. In the figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] I in the address area prepared for connecting memory.
/O device is installed, and the CPU and the above memory and I/O device are installed.
In a memory device that exchanges data with an O device, an I/O space usage memory is installed in parallel with the above I/O device, and this I/O space usage memory can handle signals of different areas at the same address. A memory device characterized in that it is responsive.