SU1633413A1 - Device for controlling exchanges between a computer and its peripherals - Google Patents

Abstract

The invention relates to real-time control systems and can be used in the construction of systems in which the peripheral devices are accessed as a memory address. The purpose of the invention is to reduce equipment. The device contains a permanent storage unit, an address decoding unit and a group of elements I. 1 s.p. f-ly, 2 ill.

Description

The invention relates to real-time control systems and can be used in the construction of systems in which the peripheral devices are accessed as a memory address.

The purpose of the invention is to reduce equipment.

FIG. 1 shows a block diagram of a device for controlling the exchange of a computer with peripheral devices; in fig. 2 - a functional block address decoding block.

The device for controlling the exchange of computers with peripheral devices contains a permanent storage unit 1, an address decoding unit 2 and a group of 3 elements I.

The address decoding unit 2 comprises an address selector 4, a group of 5 AND elements, an NOT 6 element and an AND 7 element.

The device works as follows.

In the “Input bus address of the computer mode, the address of the peripheral device is transmitted, part of the bits of which are fed to the inputs of the selector 4 of the address of the decryption unit 2

addresses. The address decryption unit 2 performs the functions of a peripheral address group decoder, and the peripheral address subarea is located in the address area allocated to the permanent storage unit 1 in the computer address space. When the address of the peripheral device transmitted by the address bus of the computer coincides with one of the addresses of the peripheral devices, the output of the address selector 4 is the address decoding unit 2, a signal is generated that allows the signals coming from the persistent storage unit 1 through the address 5 group And address decryption unit 2 peripheral sampling inputs. After the inversion of the output signal of the address selector 4 in the NOT 6 element of the address decoding unit 2, a prohibition signal is generated at the output of the AND element 7 of the address decoding unit 2, which is fed to the first inputs of a group of 3 elements AND devices. This signal prohibits the passage of information from the outputs of the permanent storage unit 1 through a group of 3 elements AND devices to the computer data bus.

(L

05 WITH

with

00

Thus, in this case, the signals at the output of the persistent storage unit I are sampling signals of a particular peripheral device. Which peripheral device will be selected is determined by programming the cells of the permanent, memory unit 1, which is assigned to the subarea of the peripheral devices. If the address on the address bus of the computer in the Input mode belongs to the address area occupied by the permanent storage unit 1, excluding addresses of peripheral devices, information is read from the permanent storage unit 1. The signal at the output of the selector 4 of the address of the address decryption unit 2 prohibits passing the sampling signals through a group of 5 elements AND the address decryption block 2 to the inputs of the peripheral devices, and its inversion coming from the output of the HE element 6 to the first input of the AND element 7 of the address decoding block 2, and the act an explicit signal is "Reading the second inlet member 7 and to provide the formation of the signal output of the AND element 7, the address decode unit 2, which permits the passage of information from the outputs of a constant storage unit 1 through group 3 elements and a computer data bus.

In the mode "Output no signal" Reading results in the prohibition signal appearing at the output element And 7 of the address decryption block 2, which, arriving at the first inputs of the group of elements And 3 of the device, prevents the information from the outputs of the permanent storage unit 1 from passing to the computer data bus at any address on the address bus of the computer. Otherwise, the operation of the block 2 of address decryption and the persistent storage unit 1 by generating signals of a sample of the required peripheral device is similar to the procedure described above for the Input mode. Coming from the group of outputs of the block 2 address decoding signals to the inputs of the sample

0

Peripheral devices provide permission to record information transmitted via a computer data bus to the required peripheral device.

Claims (2)

Invention Formula I. A device for controlling the exchange of a computer with peripheral devices, comprising a permanent storage unit, an address decryption unit, a group of elements AND, the inputs of the permanent storage unit being the device inputs for connecting a computer to the address bus and connected to the first group of information The 5 inputs of the address decryption unit, the first inputs of elements AND of the group are connected to the output of the prohibition of the address decryption unit, characterized in that, in order to reduce the equipment, in it the outputs of the permanent storage unit are connected to the second ones The 0 inputs of the AND elements of the group and the second group of information inputs of the address decryption block, the outputs of the elements of the AND group are the outputs of the device for connecting to the computer data bus, allowing 5, the address decryption unit input is a device input for connecting to a computer readout bus, the address decryption unit output group is a device output group for connecting peripheral devices to the sample inputs. thirty 2. The device according to claim 1, characterized in that the block for decoding the address comprises an address selector, a group of elements AND, an element NOT and the AND element, the first group of information inputs of the block is connected to the input selector group of the address selector, the output of which is connected to the first inputs of the AND elements of the group and through the element NOT to the first input of the AND element, the second input and output of which are respectively the enable input and the block inhibit output, the second inputs and outputs of the AND elements of the Vl - 40 group, respectively, the second group of inputs and the group of outputs of the block.