JPS6250922A - Fdd simulator - Google Patents

Abstract

PURPOSE:To execute the estimate of an FDDIF circuit quantitatively and in a single time by storing and reading data and control information to specify the pulse time interval at the RAM, converting to the read data pulse and the decoding output signal and supplying to an FDD interface (IF). CONSTITUTION:In an FDD simulator 20, from a host system 4 through a host interface circuit 107 and a RAM control signal 202 to a RAM 100, the data to specify the interval of a read data pulse 211, and the control information to generate the signal supplied to the estimate to a RAM 101 are stored. An output 206 of the RAM 100 is counted and a TC signal 208 is outputted. The TC signal 208 is extended to the constant time width by an one-shot circuit 104, and supplied to an FDDIF circuit 3 as the read data pulse. On the other hand, for the output data of the RAM 101, a decoding input signal is supplied through a decoding circuit 105 to an FDDIF circuit 3 and the circuit 3 is estimated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an FDD stain and a controller used when evaluating an FDD interface that controls an FDD (Front Disk Drive).

[Technical background of the invention and its problems]

In the development of FDD interface circuits, when evaluating the same interface circuits, conventional PDD tests were used to evaluate the interface circuits. Evaluation was performed by connecting to lli%. Figure wC3 is a connection block diagram showing a conventional evaluation means. In the figure, 1
2 is an FDD, J is an object to be evaluated, that is, an FDD interface circuit to be evaluated, and 4 is a host system such as a digital computer. 10 is FDD
Cable, 11#i-arm.

Here, the FDD interface circuit 3 was evaluated by inserting the floppy disk 1 into the FDD 2, then running a test program on the host system 4.

However, with such evaluation means, it is not possible to obtain ideal, simplified, and reproducible read data pulses from the FDD 2.

Therefore, quantitative evaluation, for example, PLL (Phaae Locked Loo) in the FDD interface circuit 3,
p) It was difficult to measure circuit tracking characteristics, peak shift Marson, etc. As a result, the evaluation actually performed mainly consisted of measuring the IJ)I error rate. However, it takes a long time to measure the read error rate.
Therefore, there was a problem in that it took a long time for development.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and provides ideal, simplified, and reproducible REET-9 data pulses to the FDD interface circuit to be evaluated.
It is an object of the present invention to provide an FDD simulator that can quantitatively perform monovaluation of a D interface circuit in a single time.

[Summary of the Invention] The FDD simulator of the present invention uses data that determines pulse time intervals given from a host device and read data/
and control information for generating a signal for evaluation excluding pulses, respectively, are stored in a RAM and read out, a pulse having a time interval according to the above data is generated, and the pulse is stretched by a predetermined time width. The IJ data pulse and the decoded output signal are used as signals for evaluation and are subject to evaluation. This configuration provides an ideal, simplified, and reproducible data pulse to the FDD interface circuit to be evaluated, thereby allowing evaluation of the FDD interface circuit. It can be done quantitatively and in a short amount of time, and the development period for FDD interface circuits can be shortened.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows an FDD stain according to an embodiment of the present invention.

FIG. 2 is a connection configuration diagram showing an evaluation means for an FDD interface using a controller. In the figure, 3, 4, 10° and 11 are the same as the above-mentioned components in Fig. 3, respectively.
is the evaluation target, that is, the FDD interface circuit to be evaluated,
4/4-Host system such as sonal computer, 1
0 is the FDD cable and 1 is the path. 2o is an FDD simulator targeted by the present invention, and its specific configuration will be described later. 2 is a link between the host system 4 and the FDD simulator 20.

FIG. 2 is a circuit diagram showing the circuit configuration of the FDD simulator 2o. In the figure, 100 is the first RAM)
, stores the data to be loaded into the counter ios. 1
01 is a second RAM that stores various control information. These RAMs 1oo and ioi are accessed from the host system 4 in FIG. 1 through the host interface circuit 107. An oscillator 102 supplies a clock signal to the counter 103.

A counter 103 loads the output data of the first RAM 100 and performs a counting operation in accordance with the clock signal output from the oscillator 102. 104 is Wangshi,
- TC output from the counter 103
The width of the (terminal count) signal is expanded to generate read data/system 211. 105 is a decoder that decodes the output data of the second RAM J OJ and sends it to the outside). Generates a signal. Decoder 105 also generates a control signal to address counter 106. 106 is an address counter, the first RA
M100,! : Generate an address to be supplied to the second RAM 10J. Normally, the address is incremented by one by the TC signal of the counter 103. However, deco/10
When a control signal is generated from 5, a different operation than normal occurs,
For example, an operation is performed to clear the count value and set the address to "0". In addition, host interface circuit 1
01 is the first RAM 1007 and the second RAM J 0
When accessing 1, no address is generated. 107 is a host interface circuit, the first ORAM 10
0 and the second RAM l OJ. When this host interface circuit 107 accesses the first RAM J 00 and the second RAM 101, an address counter disable signal is sent.

204, and invalidates the address output of the address counter 106. A data bus 200 connects the first RAM J00, the second RAM 101, and the host interface circuit No.02. 201 is an address bus, and the address output from the host interface circuit 107 or the address counter 106 is transferred to the first R bus.
AM100 and second RAM J01.

202 is a control signal for RAM J 00 and J OJ;
This is a control signal for writing and reading data between O1 and the host interface circuit J07.

A path 203 connects the host system 4 and the host interface circuit 107. 204 is an address counter disable signal that invalidates the address of the address counter 106. 205 is a signal for controlling the counting operation of the address counter. 2
06 is output from the first RAM 100, and the counter 1
This is the data that is rolled to 03. 207 is the oscillator 10
This is a clock signal output from 2. This is the TC signal of the 201Nd counter 103.

209 is various control information output from the second RAM JOJ. 210 is a trigger signal to the outside,
This signal is used for evaluation other than the read data/malus output to the FDD interface circuit. 211 is a read data pulse output from the one-shot circuit 104.

The operation of one embodiment will now be described with reference to FIGS. 1 and 2.

First, with reference to FIG. 1, the evaluation means button of the FDD interface circuit 3 using the FDD stain/receiver 20 according to the present invention will be explained. First, the host system 4 programs the FDD simulator 2o via the path 21. Next, the host system 4 executes the test program and reads the read data output from the PDD stainer 20 via the FDD interface circuit 3 and the path 1. The read data in this case is more ideal, simplified, and more reproducible than in the case shown in FIG. 3 described above, so that a constant evaluation of the PLL can be performed. In other words, by programming the FDD simulator, it is possible to extract a suitable trigger signal, so that various signal waveforms can be observed using a synchroscope or the like. In addition, since the timing of read data and pulses can be changed by a program, peak shift Marson can be measured quantitatively and accurately.

Next, the operation of the FDD simulator 2° will be explained with reference to FIG. Host system 41dm 1c.

RAM 100 and second RAM 101 f-1(D
Writing and data reading are performed. At this time, the address output of the address counter 106 is invalidated by the address counter display signal 204, and the address bus 201 is driven by the host interface circuit 107. Furthermore, the RAM control signal 202 causes the first R
It controls data writing and data reading into the AM 100 and the second RAM 10J. When writing data, data flows from the host interface circuit 107 to the first RAM J 00 and the second RAM 10 J via the data bus 200. When reading data, the first RAM 100 and the second RAM J
Data flows from OJ to host interface circuit 107 via data bus 200.

The first RAM 100 has a read data pulse 211
Data for determining the occurrence interval is stored. The counter 103 low-levels the data 206 output from the first RAM 200 and increments the count by the clock signal 207 generated by the s oscillator 102 . The counter 103 generates a TC signal 208 when a predetermined count ends. The counter 103 itself loads the next data in response to the TC signal 208. At the same time, the TC signal 20B is clocked to the address counter 106.

The address counter 106 increments the address by one and outputs the new address to the address path 201. As a result, the first RAM 100 and the second RAM 101 output the next data 206 and 209, respectively. Further, the TC signal 208 is the one-shot circuit 1
04, is expanded to a certain time width, and is output as read data pulse 211.

In this way, the read data/mother pulse 21 can be generated at the programmed timing. On the other hand, the second RAM J01 stores various control information, which is output from the RAM J01. The generated data 209 passes through the decoder 105 and becomes an external signal and an FDD interface signal 210 other than the 17p data signal.

Thereby, various signals for evaluation including read data and base pulses can be generated at programmed timings. Further, an address counter control signal 205 is output from the decoder 105, and the address counter 10
Controls the counting operation of 6. This allows you to change the sequence of addresses that are generated.

As described above (use the FDD simulator 20 shown in FIG. 2 above in evaluating the FDD interface circuit), the PL in the FDD interface circuit to be evaluated is
Quantitative evaluation of the L circuit can be performed. In addition, peak shift mercury can be measured with high accuracy. As a result, FD
The development period for the D interface circuit can be shortened.

The above-mentioned FDD simulator is for evaluating the FDD interface circuit connected to the host system such as the No-Archive-Sonal Combi and the Yu-Yu, but there is also a need to measure the tracking characteristics of the PLL. It is a powerful tool in various fields.

〔Effect of the invention〕

As detailed above, according to the FDD spotter of the present invention, there is provided a first storage section that stores data that determines pulse time intervals, and a pulse generator that outputs pulses at time intervals according to the data read from the first storage section. a pulse generation circuit that generates a pulse;
The pulse generated by this pulse generation circuit is stretched over a predetermined time width and a read data pulse is output.
a base pulse output circuit, a second storage section that stores control information for generating the above-mentioned P data/signals used for evaluation excluding the pulses; The present invention is equipped with a decoder for decoding the data, and supplies the signal output from the pulse output circuit and the decoder to the FDD interface circuit to be evaluated. By providing ideal, simplified, and reproducible data to the target FDD interface circuit, it is possible to evaluate the FDD interface circuit quantitatively and in a single time. , 9 The development period for FDD interface circuits can be shortened.

[Brief explanation of the drawing]

Figure 1 shows nine FDs using the FDD stain and rotor according to the present invention.
FIG. 2 is a circuit diagram showing the circuit configuration of an FDD smitter according to an embodiment of the present invention, and FIG. 3 is a diagram showing the conventional FDD interface evaluation means. , is a diagram. 3...-FDD interface circuit (evaluation target), 4
...Host system, 10...FDD cable, 1
1゜21.../yasu, 20...FDD stain, rater, 100゜101...RAM, J0J river counter, 1
04...One-shot circuit, 105...Decoder, 10
6... Address counter, 107... Host interface circuit, 200... Data bus, 201...
・Arres/quantity.

Claims (1)

[Claims] a first storage section that stores data that determines pulse time intervals; a pulse generation circuit that generates pulses at time intervals according to the data read from the first storage section; a pulse output circuit that outputs an enlarged read data pulse with a predetermined time width; a second storage unit that stores control information for generating signals for evaluation other than the read data pulse; and a decoder for decoding data read from the storage section, and supplying read data pulses output from the pulse output circuit and signals output from the decoder to an FDD interface circuit to be evaluated. FDD simulator.