JPS6250922A - Fdd simulator - Google Patents

Fdd simulator

Info

Publication number
JPS6250922A
JPS6250922A JP60189904A JP18990485A JPS6250922A JP S6250922 A JPS6250922 A JP S6250922A JP 60189904 A JP60189904 A JP 60189904A JP 18990485 A JP18990485 A JP 18990485A JP S6250922 A JPS6250922 A JP S6250922A
Authority
JP
Japan
Prior art keywords
circuit
ram
signal
fddif
fdd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60189904A
Other languages
Japanese (ja)
Inventor
Nobutaka Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60189904A priority Critical patent/JPS6250922A/en
Publication of JPS6250922A publication Critical patent/JPS6250922A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To execute the estimate of an FDDIF circuit quantitatively and in a single time by storing and reading data and control information to specify the pulse time interval at the RAM, converting to the read data pulse and the decoding output signal and supplying to an FDD interface (IF).
CONSTITUTION: In an FDD simulator 20, from a host system 4 through a host interface circuit 107 and a RAM control signal 202 to a RAM 100, the data to specify the interval of a read data pulse 211, and the control information to generate the signal supplied to the estimate to a RAM 101 are stored. An output 206 of the RAM 100 is counted and a TC signal 208 is outputted. The TC signal 208 is extended to the constant time width by an one-shot circuit 104, and supplied to an FDDIF circuit 3 as the read data pulse. On the other hand, for the output data of the RAM 101, a decoding input signal is supplied through a decoding circuit 105 to an FDDIF circuit 3 and the circuit 3 is estimated.
COPYRIGHT: (C)1987,JPO&Japio
JP60189904A 1985-08-30 1985-08-30 Fdd simulator Pending JPS6250922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60189904A JPS6250922A (en) 1985-08-30 1985-08-30 Fdd simulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60189904A JPS6250922A (en) 1985-08-30 1985-08-30 Fdd simulator

Publications (1)

Publication Number Publication Date
JPS6250922A true JPS6250922A (en) 1987-03-05

Family

ID=16249144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60189904A Pending JPS6250922A (en) 1985-08-30 1985-08-30 Fdd simulator

Country Status (1)

Country Link
JP (1) JPS6250922A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04102515U (en) * 1991-02-06 1992-09-03

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53145535A (en) * 1977-05-25 1978-12-18 Toshiba Corp Universal interface
JPS5968034A (en) * 1982-10-05 1984-04-17 Kenji Kinoshita Input and output port simulator for microcomputer developing device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53145535A (en) * 1977-05-25 1978-12-18 Toshiba Corp Universal interface
JPS5968034A (en) * 1982-10-05 1984-04-17 Kenji Kinoshita Input and output port simulator for microcomputer developing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04102515U (en) * 1991-02-06 1992-09-03

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