RU1807525C - Device for main storage diagnostics - Google Patents

Abstract

The invention relates to computer technology and can be used in the development of random access memory with integrated diagnostics in integrated form. The aim of the invention is to increase the reliability of diagnostic monitoring. The device comprises a test driver, a pulse generator, a comparison unit, the outputs of which are connected to the information inputs of the error distribution driver, the outputs of which are connected to the inputs of the error distribution memory, address and data conditioners, controlled inverters, an EXCLUSIVE OR NOT. When tested in the error distribution memory block, a summary memory error map is recorded, which is then output to the processor for processing. 2 ill.

Description

ate

with

The invention relates to computer technology and can be used in the development of random access memory with integrated diagnostics in integrated form.

The aim of the invention is to increase the reliability of diagnostic monitoring.

In FIG. 1 shows a diagram of a device for diagnostic monitoring of random access memory; in FIG. 2 is an error distribution fixation block.

The device contains a counter 1 of low addresses, a counter of 2 high addresses, a counter 3 of a test driver, a 4 pulse generator, a group of controlled inverters 5. a comparison block b, a block 7 for generating an error distribution, a block 8 for memory of an error distribution, an EXCLUSIVE OR NOT 9 bus formers

data 10, 11 and addresses 12, 13, input 14 of the initial setting signal, input 15 of the start signal, input 16 of the read signal of the error distribution, output 17 of the device ready signal, output 18 of the read / write signal to the drive, outputs 19 low addresses, outputs 20 high addresses, output 21 of the access signal to the drive, outputs - inputs 22 data. Blocks 1-3 form a test shaper.

The block 7 for generating the distribution of errors at input 23 is connected to the output of the lowest order of the counter 1 of the lowest addresses, at input 24, to the output N-2 of the category of the counter 2 of the highest addresses, at input 25, to the output of the pulse generator 4, and at input 26, to the output signal overflow counter 1 low addresses at the inputs 27 to the outputs of the block comparison 6 at the outputs 28 to the information inputs of the block 8 memory error distribution.

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Joint venture

Yu

Joint venture

Block 7 of the error distribution generator (Fig. 2) comprises a trigger 29, a register 30 consisting of l-triggers, an AND element 31, an OR element 32, a pulse shaper 33.

Test generator counter 3 is used to generate a pseudo random data test sequence and can be implemented by known methods.

The error distribution memory unit 8 is a stack and can be executed according to the scheme.

The device operates as follows.

After the power is turned on, before starting work, the device receives the initial setting signal 14, which sets the address counters 1 and 2 to the zero state, resets the test generation counter 3, sets trigger 29 to the Log state. Oh, the register 30 and the error distribution memory block 8 are reset. In the diagnostic mode, a trigger signal is received at the input 15 of the device, which allows the pulse generator 4 to work and serves as a sample signal for address shapers 12,13 and data 10.

Pulse generator 4 provides switching of the counter 1 of the lowest addresses, the low-order of which is a read-write signal for random access memory (RAM). Enumerating the remaining addresses of this counter allows us to test the first linear OP. The pulse generator 4 also provides data enumeration in the counter 3 of the test generator, which generates a pseudo-random sequence of codes for implementing the simulated March test algorithm for Multi-bit memory. Data from the meter 3 of the test driver through the controlled inverters 5 is fed to the bus data driver 10, which transfers data to the memory of the memory 22. The controlled inverters 5 are controlled using the element EXCLUSIVE OR NOT, depending on the Read mode or Recording to and from the N-2 bit of the high-order counter 2, which characterizes the parity of the sequence number of the test cycle. The low-order bit of the low-order counter 1, which characterizes the read-write mode, blocks the sampling signal of the data shaper 10 in the READ mode. The pulse generator 4 also generates a signal for accessing the memory 21.

Thus, for each address of the OP line, depending on the status of the bits of the counter of lower addresses and the signal of overflow of the counter of high bits

The diagnostic device initiates two calls: reading a direct (inverse) code. And writing an inverse (direct) code. In the reading cycles, the data from the OP via the bi-directional buses 22 are sent to the comparison unit 6, where they are compared with the standard generated at the outputs of the inverters controlled by the counter 3 of the test shaper. The resulting comparison vector 27 arrives

to an error distribution fixing unit 7, which operates as follows.

Block 7 is based on a diagnostic register 30, each bit of which i represents a 1-flip-flop, gated by signal 25 from pulse generator 4 when there is a sign of valid data from the output of the trigger 29 and a sign of a read cycle from the output 23. The need to introduce a trigger 29 due to the fact that

0 initially, random information is present in the drive of the tested OP and the reading results on the first pass of the test do not carry useful information. With a complete enumeration of all addresses of the OP to N-3

On the 5th output of counter 2 of the highest addresses, signal 24 appears, which sets trigger 29 to the Log state. 1, which corresponds to the appearance of a sign of validity of the data, the same signal 24 out of 0, changes the logical state at one of the inputs of the element EXCLUSIVE OR NOT, which leads to the fact that if at the first pass we read the direct code and write the inverse then at

5 implementation of the second pass we will

read the inverse code and write right,

.At the end of the passage of each line OP

from overflow output of low counter

A signal 26 arrives at the address, which is run by the driver 33 and the contents of register 30 are reset on the trailing edge after it was rewritten to the error distribution memory 8 on the last edge of signal 26. After four passes of the test were performed in the high order of the highest counter of bits 2, the ready signal 17 will appear. It will simultaneously turn off the pulse generator 4 and inform the processor about the completion of the diagnostics. To transmit to the processor after testing, the error distribution matrix stored in block 8 of the error distribution matrix, an active signal must be supplied. Output 16 is so much

5 times how many rulers the OD has, the Output signal will be a read signal from the error distribution memory block and a sample signal of the bus data former 4.

Thus, the proposed device for diagnostic monitoring provides a distribution of errors of full dimension and can be used to diagnose OP to the level of microcircuits and communications.

Claims (2)

1. A device for diagnostic control of random access memory, comprising a test driver, error distribution driver, first group data drivers, first group address drivers and a comparison unit, the first group of inputs of which are connected to the outputs of the first group of data drivers and are information inputs the outputs of the device, the reset input of which is the reset input of the error distribution driver, the information inputs of which are connected to the outputs of the comparison unit, and the outputs of the addressers of the first group are the outputs of the most significant bits of the device address, characterized in that, in order to increase the reliability of the diagnostic control, a pulse generator, an EXCLUSIVE OR NOT element, a group of controlled inverters, an error distribution memory block, data shapers are introduced into it the second group and the address formers of the second group, the first input of the element EXCLUSIVE OR NOT, the write enable input of the error distribution former, the information input of the first address former of the second group The resolvers of the first group of data are combined and connected to the first output of the test shaper, the outputs of the first group of which are connected to the information inputs of the second group of address shapers, starting from the second, the outputs of which are the low-order outputs of the device address, the read-write output of which is the output of the first driver of the address of the second group, the outputs of the second group of the driver of the test are connected to the information inputs of the drivers of the first group, the second input of the element The EXCLUSIVE OR NOT and the installation input of the error distribution driver are combined and connected to the second output of the test driver, the third output of which is connected to the -first input of the pulse generator and is the readiness outputs of the device, the input of which is the second input of the pulse generator, the output of which connected to the combined sync inputs of the test driver and the error distribution driver and is the output of the device access, the intermediate reset input of the error distribution driver and the input the records of the error distribution memory block are combined and connected to the fourth output of the test shaper, the information inputs and outputs of the error distribution memory block are connected respectively to the outputs of the error shaper and the information inputs of the second data shapers, the outputs of which are connected to the inputs of the first group of the comparison block, the outputs the third group of the test driver is connected to the first inputs of the controlled inverters of the group, the second inputs of which are combined and connected to the output of the element EXCLUSIVELY E OR NOT, the information inputs of the first group of data shapers and the inputs of the second group of the comparison unit are combined and connected to the corresponding outputs of the controlled inverters, the control inputs of the address shapers of the first and second groups and the data shapers of the first and second groups are connected to the device start input, input the readings of the error distribution memory block and the control input of the second data shapers are combined and are the control input of the device output, the reset inputs of the test shaper and the memory block ti error distribution unit connected to the input reset. 2. The device according to claim 1, characterized in that the error distribution generator comprises a trigger, an AND element, an OR element, a pulse generator and a register, wherein the trigger input is the driver input, the trigger reset input is the driver reset input and connected to the first input of the OR element, the second input of which is connected to the output of the pulse former, the input of which is the input of the intermediate reset of the driver, the first input and output of the And element are connected respectively to the output of the trigger clock terminal of register ra and whose reset input is connected to the output of the OR gate, second and third inputs of AND gate are respectively write enable input and the clock shaper, data inputs and outputs of the register are respectively data inputs and outputs shaper. FIG. / gz ft Ј3 sixteen Conclusion 27 Ј YaR 50 :