JPS6247164A - Junction type field effect transistor - Google Patents

Abstract

PURPOSE:To accurately obtain a channel length by forming a channel region of 2-layer structure of the first and second conductivity types when forming a channel interposed between a source and a drain in J-FET, and forming source and drain regions at both end sides. CONSTITUTION:An oxide film 2 is coated on the surface of a P-type Si substrate 1, a window is opened, an Si layer made of N-type layer 3 and P-type layer 4 to partly become a channel region later is laminated on the exposed substrate 1 and epitaxially grown. Then, N<+> type source and drain regions 5 are diffused at both ends of the laminate while intruding to the lower layer 3, and the laminated disposed between the regions is used as a channel region. Thus, the channel length can be accurately formed in the desired length, and the manufacture can be simplified without double diffusion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a junction field effect transistor.

[Background technology]

Conventionally, as shown in Fig. 6, an N layer (■) and a P layer (■) are sequentially formed on a P substrate (■) in a double diffusion structure, and then the P substrate (■) and the P layer (■) are formed.
Goo 1. The N layer (2) is formed by epitaxial growth of the N type on the P substrate (2), as shown in FIG. A junction type field effect transistor is known in which a P layer (2) is diffused from the surface of the layer (2), the P substrate (2) and the P layer (2) serve as gates, and both ends of the N layer (2) serve as a source (2) and a drain (3).

In these junction field effect transistors,
Boron impurity diffusion is used to form the P layer (2) which becomes the upper gate, and in normally-on type devices, the channel which determines the threshold voltage Vth (gate voltage required to turn off) [There was a drawback that formation of 11h was difficult.

[Purpose of the invention]

An object of the present invention is to provide a junction field effect transistor in which a channel between gates can be formed with high precision.

[Disclosure of the invention]

The gist of this invention is that a second layer of a second conductivity type, which is formed by epitaxial growth on a substrate of a first conductivity type, and a third layer of a first conductivity type, which is a gate, are sequentially laminated. This is a junction type field effect I-transistor characterized by forming a highly doped fourth layer of the second conductivity type for contact to the second layer at both ends of the three layers.

An embodiment of a junction type field effect transistor according to the present invention will be described below with reference to the manufacturing process and completed drawings shown in FIGS. 1 to 5.

In this example, silicon P is used as the substrate of the first conductivity type.
A mold substrate (1) is used. Further, an N-type silicon layer (3) is used as the second layer of the second conductivity type, a ■) type silicon layer (4) is used as the third layer of the first conductivity type, and a fourth layer of the high concentration second conductivity type is used. N layer (5) is used.

As shown in FIG. 1, a window (6) is opened in the surface oxide film (2) of a commercially available silicon P-type substrate die.

An N-type silicon layer (3) is epitaxially grown in the area where this window (6) is opened. FIG. 2 shows this state.

A P-type silicon layer (4) is further epitaxially grown on the N-type silicon layer (3). FIG. 3 II shows this situation.

The steps shown in FIGS. 2 and 3 are performed using selective epitaxial growth technology.

N-type silicon layer (3) on both ends of P-type silicon layer (4)
An N1 layer (5) is formed by diffusing N'' so as to reach .

Figure 4 shows the condition of the car.

Each N1 layer (5) thus formed is used for a source or 1'-rain contact. Finally, the entire surface is covered with an oxide film (7), and each N layer (5)
An opening 1 is provided in the center of the - and P-type silicon layer (4) to connect the source, F' L-in, and gate electrodes (8) and (9).
), (10) are formed.

The gate electrode (11) that is a pair of the gate electrode (10) is P
A normally-on type junction field effect transistor is formed on the back surface of the mold substrate (1) in the following manner.

1? In a junction field effect transistor formed like a silicon substrate, the channel height is determined only by the growth height of an N-type silicon layer (3) epitaxially grown on a [ )-type silicon substrate (1).

Furthermore, even if N" is diffused, the temperature remains at 900℃.
Since this is carried out under certain conditions, the diffusion from the p-type silicon layer (4) can be ignored compared to the height of the n-type silicon layer (3), that is, the channel height.

Note that, unlike Example 1, an N-type substrate is used as the first conductivity type, a P-type silicon layer is used as the second layer of the second conductivity type, and an N-type silicon layer is used as the third layer of the first conductivity type. Of course, a P layer may be used as the fourth layer of the second conductivity type with high concentration.

〔Effect of the invention〕

As shown in FIG. 3, the channel height of the junction field effect transistor according to the present invention is determined by the height of the second layer of the second conductivity type, which is selectively epitaxially grown on the substrate of the first conductivity type. Therefore, the inside of the channel (channel height) between the gates can be formed with high precision.

Further, since the junction type field effect transistor according to the present invention does not use the conventional double diffusion method during manufacturing, it has the advantage that it can be manufactured with fewer thermal diffusion steps.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views showing one embodiment of the present invention,
FIGS. 6 and 7 are sectional views showing conventional examples, respectively. (1)...P-type substrate, (3)...N-type silicon layer,
(4)...P-type silicon layer, (5)...N゛ layer, (
7)...Oxide film, (8)...(9)...(10)
...(11)...electrode.

Claims (1)

[Claims] (1) A second layer of the second conductivity type that will become a channel and a third layer of the first conductivity type that will become a gate are formed by epitaxial growth on a substrate of the first conductivity type, and at both ends of the third layer, A junction type field effect transistor characterized in that a fourth layer of a second conductivity type with a high concentration is formed for contact reaching the second layer.