JPS6246080B2 - - Google Patents

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Publication number
JPS6246080B2
JPS6246080B2 JP13532581A JP13532581A JPS6246080B2 JP S6246080 B2 JPS6246080 B2 JP S6246080B2 JP 13532581 A JP13532581 A JP 13532581A JP 13532581 A JP13532581 A JP 13532581A JP S6246080 B2 JPS6246080 B2 JP S6246080B2
Authority
JP
Japan
Prior art keywords
layer
wiring pattern
wiring board
circuit
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13532581A
Other languages
Japanese (ja)
Other versions
JPS5835998A (en
Inventor
Kenji Oosawa
Hajime Tokumitsu
Takao Ito
Juji Ikegami
Masayuki Oosawa
Keiji Kurata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP13532581A priority Critical patent/JPS5835998A/en
Publication of JPS5835998A publication Critical patent/JPS5835998A/en
Publication of JPS6246080B2 publication Critical patent/JPS6246080B2/ja
Granted legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 本発明は、リジツト(硬性)回路部分とフレキ
シブル(柔性)回路部分を有して成る多層配線基
板の製法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer wiring board having a rigid circuit portion and a flexible circuit portion.

リジツト配線基板を他の配線基板に電気的に接
続する場合、その接続端部においてはフレキシブ
ル部分であることが望ましい。例えば第1図に示
すようにリジツト配線基板1上にフレキシブル回
路部分2を積層した構成とすれば、その接続端部
が柔軟性を有することによつて、他の配線基板4
との相互接続が容易且つ確実になると共に、両基
板1及び4の配設場所も自由度が大きくなる等の
利点がある。なお、5及び6は夫々の基板の回路
パターン、7は開口部を通して充填された半田等
の導電性物質を示す。
When electrically connecting a rigid wiring board to another wiring board, it is desirable that the connection end be a flexible portion. For example, if a flexible circuit part 2 is laminated on a rigid wiring board 1 as shown in FIG.
There are advantages such as easy and reliable interconnection with the substrates 1 and 4, and a greater degree of freedom in the placement of both substrates 1 and 4. Note that 5 and 6 are circuit patterns of the respective substrates, and 7 is a conductive material such as solder filled through the opening.

従来のこの種の多層回路基板の製法としては、
例えば第2図A及びBに示すように硬質ベークラ
イト基板8の一主面に第1層回路9を形成してな
るリジツト回路部分10と、ポリイミドフイルム
11上に銅箔による第2層回路12を形成したフ
レキシブル回路部分13とを夫々別体に設け、そ
のフレキシブル回路部分13の接続部(開口部)
14をドリルで孔明し、裏面に接着剤15を塗布
してリジツト回路部分10に張り合せて後、接続
部14に半田16を充填すると共に所要回路の接
続部を通る貫通孔17を穿け所要の電気部品18
を接続するようにしている。又は、第3図A及び
Bに示すように、ポリイミドフイルム11にスル
ホールメツキ19を用いた両面回路20及び21
を形成してなるフレキシブル配線基板22を設
け、これを接着剤15を介して硬質ベークライト
基板8に張り合せ、しかる後ドリルにより所要回
路の接続部を通る貫通孔17を穿け所要の電気部
品18を接続するようにしている。
The conventional manufacturing method for this type of multilayer circuit board is as follows:
For example, as shown in FIGS. 2A and 2B, a rigid circuit section 10 is formed by forming a first layer circuit 9 on one main surface of a hard Bakelite substrate 8, and a second layer circuit 12 made of copper foil is formed on a polyimide film 11. The formed flexible circuit portions 13 are provided separately, and the connecting portions (openings) of the flexible circuit portions 13 are provided separately.
14 with a drill, apply adhesive 15 to the back side and attach it to the rigid circuit part 10, then fill the connection part 14 with solder 16 and drill a through hole 17 through the connection part of the required circuit. Electrical parts 18
I am trying to connect. Alternatively, as shown in FIGS. 3A and 3B, double-sided circuits 20 and 21 using through-hole plating 19 on polyimide film 11
A flexible wiring board 22 is provided, which is bonded to a hard Bakelite board 8 via an adhesive 15, and then a through hole 17 is drilled through the connection portion of the required circuit to connect the required electrical component 18. I'm trying to connect.

しかるに、前者の場合には、リジツト回路部分
10とフレキシブル回路部分13の張り合せ精度
が悪いこと(張り合せ前にフレキシブル回路部分
に孔明が必要)、フレキシブル回路部分13の回
路形成ではリジツト性がないために取扱いが難か
しいこと、第1層回路9と第2層回路12との半
田接続が1穴ずつ手で半田充填して行なわれるた
めに量産性がないこと、孔明けが困難で回路同志
を接続することがむずかしいこと、ドリルによる
孔明けのために孔径が小さくできず回路12の占
有面積が大きくなり高密度化が阻害されること、
連続生産プロセス化が出来ない等の問題点があ
る。
However, in the former case, the accuracy of bonding the rigid circuit portion 10 and the flexible circuit portion 13 is poor (the flexible circuit portion requires drilling before bonding), and the circuit formation of the flexible circuit portion 13 lacks rigidity. The solder connections between the first layer circuit 9 and the second layer circuit 12 are made by manually filling each hole with solder, which is not suitable for mass production. It is difficult to connect the circuits 12, and the hole diameter cannot be made small due to drilling, which increases the area occupied by the circuit 12 and impedes high density.
There are problems such as the inability to create a continuous production process.

又、後者の場合には、フレキシブル配線基板2
2の製造プロセスが複雑な上、排水処理設備が必
要であるため好ましくないこと、回路形成がリジ
ツト性がないため取扱いが困難であること、フレ
キシブル配線基板にドリルで孔明けを行うため孔
径に限度があり、高密度の回路形成が出来にくい
こと、連続生産性プロセス化が出来ないこと、等
の問題点があつた。
In the latter case, the flexible wiring board 2
The manufacturing process of No. 2 is complicated and requires wastewater treatment equipment, which is undesirable; the circuit formation is not rigid, making it difficult to handle; and the holes are drilled into the flexible wiring board, so there is a limit to the hole diameter. However, there were problems such as the difficulty in forming high-density circuits and the inability to create a process with continuous productivity.

本発明は、上述の問題点を解決し、量産性に適
し且つ高密度の回路形成を可能にした多層配線基
板の製法を提供するものである。
The present invention solves the above-mentioned problems and provides a method for manufacturing a multilayer wiring board that is suitable for mass production and enables high-density circuit formation.

以下、第4図A〜Eを用いて本発明による多層
配線基板の製法を説明する。
Hereinafter, a method for manufacturing a multilayer wiring board according to the present invention will be explained using FIGS. 4A to 4E.

本発明は、先づ第4図Aに示すように、例えば
紙フエノール、紙エポキシ又はガラスエポキシ等
のリジツト絶縁基板31上に銅箔32を張り合せ
てなる所謂銅張り積層板33を用意し、この銅箔
32を選択エツチングして第1層の配線パターン
34を形成すると共に、この配線パターン34を
有した第1の部分35と〓後これから分離される
第2の部分36との間に機械的力により分離され
得る分離手段37を設ける。この分離手段37と
しては図示の例では等間隔で所定の孔を明けた所
謂ミシン目38をもつて構成しているが、その他
裏面に分離線に沿つてV型溝を設けるようにして
も可能である。
In the present invention, first, as shown in FIG. 4A, a so-called copper-clad laminate 33 is prepared by laminating a copper foil 32 on a rigid insulating substrate 31 made of, for example, paper phenol, paper epoxy, or glass epoxy. This copper foil 32 is selectively etched to form a first layer wiring pattern 34, and a mechanical part is formed between a first part 35 having this wiring pattern 34 and a second part 36 which is later separated from the first part 35. Separation means 37 are provided which can be separated by force. In the illustrated example, this separation means 37 is constructed with so-called perforations 38, which are holes made at regular intervals, but it is also possible to provide V-shaped grooves along the separation line on the back surface. It is.

次に、第4図Bに示すように基板31の第2の
部分36上に離型印刷又はテーピングによつて離
型層39を形成する。離型印刷としては例えばシ
リコン樹脂液を10%以上含んだエポキシ樹脂、フ
エノール樹脂塗料によるシリコン系インキ、或は
テフロン粉末(粒径5〜50μ)を含んだエポキ
シ、フエノール樹脂によるインキ等を用い得る。
又、テーピングとしては、アクリルエマルジヨン
系の接着剤をコーテイングしたシリコンフイルム
(シリコンテープ)あるいはテフロンフイルム
(テフロンテープ)等を用い得る。
Next, as shown in FIG. 4B, a release layer 39 is formed on the second portion 36 of the substrate 31 by release printing or taping. For release printing, for example, epoxy resin containing 10% or more silicone resin liquid, silicone ink using phenol resin paint, epoxy containing Teflon powder (particle size 5 to 50μ), ink using phenol resin, etc. can be used. .
Further, as the taping, a silicone film (silicon tape) or a Teflon film (Teflon tape) coated with an acrylic emulsion adhesive may be used.

次に、第4図Cに示すように基板31上のほぼ
全面、即ち第1層配線パターン34の〓後形成す
る第2層配線パターンとの接続部分40、電気部
品接続部分(図示せず)、さらには他の配線基板
との接続部に対応した部分41を除く全面に、印
刷によつて可撓性を有する絶縁樹脂層42を印刷
によつて形成する。この絶縁樹脂層42として
は、例えばエポキシポリアミド、エポキシアクリ
レート、ウレタンアクリレート、又はブレンド樹
脂等を用い得る。
Next, as shown in FIG. 4C, almost the entire surface of the substrate 31, that is, the connection portion 40 with the second layer wiring pattern to be formed after the first layer wiring pattern 34, and the electrical component connection portion (not shown) are formed. Further, a flexible insulating resin layer 42 is formed by printing on the entire surface except for a portion 41 corresponding to a connection portion with another wiring board. As this insulating resin layer 42, for example, epoxy polyamide, epoxy acrylate, urethane acrylate, blend resin, or the like can be used.

次に、絶縁樹脂層42上の全面に導電箔層例え
ば銅箔を張り合せて後、第4図Dに示すように銅
箔を選択エツチングして第2層の配線パターン4
3及び第1層配線パターン34の接続部40に到
る開口部44を形成する。なお、第2層配線パタ
ーン43の開口部44においては、銅箔を張り合
せた際の接着剤50が残つているので、さらにそ
の部分の接着剤を有機溶剤で除去し、第1層配線
パターン34の接続部40を臨ましめる。この第
2層配線パターン43の形成時に同時に〓後他の
配線基板との接続部分に対応する位置に開口部5
1を形成するを可とする。
Next, after pasting a conductive foil layer, for example, copper foil, on the entire surface of the insulating resin layer 42, the copper foil is selectively etched as shown in FIG. 4D to form the second layer wiring pattern 4.
3 and an opening 44 reaching the connection portion 40 of the first layer wiring pattern 34 is formed. Note that in the opening 44 of the second layer wiring pattern 43, the adhesive 50 from when the copper foil was pasted remains, so the adhesive in that area is further removed with an organic solvent and the first layer wiring pattern 43 is removed. 34 connection parts 40 are exposed. At the same time when this second layer wiring pattern 43 is formed, an opening 5 is formed at a position corresponding to the connection part with another wiring board.
It is possible to form 1.

次に、第4図Eに示すように第2層配線パター
ン43の開口部44内に導電性物質45を充填し
て上下の配線パターン43及び34を接続する。
しかる後、機械的手段によつて基板31のミシン
目38より分離して第2の部分36を除去する。
この第2の部分36は離型層39によつて絶縁樹
脂層42からも離型する。
Next, as shown in FIG. 4E, the opening 44 of the second layer wiring pattern 43 is filled with a conductive material 45 to connect the upper and lower wiring patterns 43 and 34.
Thereafter, the second portion 36 is separated from the perforation 38 of the substrate 31 by mechanical means and removed.
This second portion 36 is also released from the insulating resin layer 42 by the release layer 39 .

導電性物質45としては、ガリウム合金、半田
デイツプ、銀ペースト、CU、Zn、Sn等の低融点
金属による金属溶射等による導電材を用い得る。
特に、ガリウム合金の場合は、常温所謂30℃以
下で液状を呈するガリウムGaと、このガリウム
と共晶する金属と、ガリウムと合金化し融点を上
昇させ得る金属粉(単体の金属粉、もしくは合金
粉)との混合物により構成する。このガリウム合
金の導電性物質は、当初作業温度においてペース
ト状をなし、その後、経時的に合金化し凝固する
性質を有している。このガリウム合金を用いると
きは、銀ペイントに於けるような銀のマイグレー
シヨンの問題が回避され、又導電性もCuメツキ
と同等になるなど品質のよい回路形成が可能とな
る。
As the conductive material 45, a conductive material such as a gallium alloy, a solder dip, a silver paste, a metal spraying of a low melting point metal such as CU, Zn, or Sn can be used.
In particular, in the case of gallium alloys, gallium Ga, which is liquid at room temperature below 30°C, a metal that is eutectic with this gallium, and a metal powder (single metal powder or alloy powder) that can be alloyed with gallium and raise its melting point. ). This gallium alloy conductive substance has the property of initially forming a paste-like form at the working temperature, and then becoming alloyed and solidifying over time. When this gallium alloy is used, the problem of silver migration that occurs with silver paint is avoided, and the conductivity is equivalent to that of Cu plating, making it possible to form high-quality circuits.

基板31の第2の部分36を分離する方法とし
ては、例えば第5図A及びBに示すように、導電
性物質45を充填した後の積層体52をローラ5
3及び54間に挿通し、第2の部分36を下方よ
り押圧子55にて押し上げればミシン目38より
容易に分離される。
As a method for separating the second portion 36 of the substrate 31, for example, as shown in FIGS.
3 and 54, and push up the second portion 36 from below with the presser 55, it can be easily separated from the perforation 38.

斯くすることにより、第4図Eに示すように第
1層配線パターン34を有したリジツト回路部分
56上に、その端縁より他の配線基板との接続端
部57が突出するように、第2層配線パターン4
3を有したフレキシブル回路部分58が積層され
て成る目的の多層配線基板59を得る。この多層
配線基板59を他の配線基板に接続するときは、
前述の第1図と同様そのフレキシブル回路部分5
8の接続端部57を他の配線基板4(第1図参
照)の接続端部上に第2層配線パターン43の開
口部51を他の配線基板4の所要の回路パターン
に合せるように重ね合せ、その開口部51内に導
電性物質45を充填するようになす。
By doing so, as shown in FIG. 4E, a first layer is formed on the rigid circuit portion 56 having the first layer wiring pattern 34 so that the connection end 57 to another wiring board protrudes from the edge thereof. 2 layer wiring pattern 4
A target multilayer wiring board 59 is obtained in which flexible circuit portions 58 having a thickness of 3 are laminated. When connecting this multilayer wiring board 59 to another wiring board,
The flexible circuit portion 5 is similar to that shown in FIG. 1 above.
8 over the connection end 57 of another wiring board 4 (see FIG. 1) so that the opening 51 of the second layer wiring pattern 43 is aligned with the required circuit pattern of the other wiring board 4. Then, the opening 51 is filled with the conductive material 45.

上述せる本発明製法によれば、リジツト絶縁基
板31上に第1層配線パターン34を形成し、さ
らにこの上に可撓性を有する絶縁樹脂層42を介
して第2層配線パターン43を形成して後、絶縁
基板31の他配線基板との接続部分に対応する第
2の部分36を分離除去するようにしたことによ
り、高密度な回路形成と同時に、生産性よくこの
種の多層配線基板が製造できる。特に、両配線パ
ターン34及び43間の接続に供する開口部44
の形成は、従来のドリル工程を用いずに化学的エ
ツチングで形成するので、孔径が微細となり、従
つて接続部を含む配線パターン34,43の占有
面積が小さくて済み、高密度化が可能となる。し
かも、リジツト基板の状態で開口部44の形成が
できるので製造工程時の取り扱いが容易となる。
According to the manufacturing method of the present invention described above, a first layer wiring pattern 34 is formed on a rigid insulating substrate 31, and a second layer wiring pattern 43 is further formed thereon via a flexible insulating resin layer 42. By separating and removing the second portion 36 corresponding to the connecting portion of the insulating substrate 31 with other wiring boards, this type of multilayer wiring board can be manufactured with high productivity while simultaneously forming high-density circuits. Can be manufactured. In particular, the opening 44 used for connection between both wiring patterns 34 and 43
Since the holes are formed by chemical etching without using the conventional drilling process, the hole diameter is fine, and therefore the area occupied by the wiring patterns 34 and 43 including the connection parts is small, making it possible to increase the density. Become. Moreover, since the opening 44 can be formed in the rigid substrate state, handling during the manufacturing process is facilitated.

又、絶縁樹脂層42により両配線パターン34
及び43間の間隔が小さいために導電性物質45
例えばガリウム合金の充填に際しては、印刷手段
により容易に充填できるので連続生産が可能とな
り大量生産に好適である。
In addition, both wiring patterns 34 are connected by the insulating resin layer 42.
and 43 because the distance between them is small, the conductive material 45
For example, when filling with gallium alloy, it can be easily filled by printing means, which enables continuous production and is suitable for mass production.

また、他の配線基板との接続も、予め接続端部
に予め開口部51を設けることが出来るので、こ
の開口部51を使用して容易に接続することが出
来る。
Furthermore, since an opening 51 can be provided in advance at the connection end for connection to another wiring board, the connection can be easily made using this opening 51.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の説明に供する互に異なる配線
基板の線続状態を示す斜視図、第2図A及びBと
第3図A及びBは夫々従来の多層配線基板の製法
例を示す工程図、第4図A〜Eは本発明製法を示
す工程図、第5図A及びBは本発明の分離工程の
一例を示す断面図である。 31はリジツト絶縁基板、34は第1層配線パ
ターン、35は第1の部分、36は第2の部分、
38はミシン目、39は離型層、43は第2層配
線パターン、44は開口部である。
FIG. 1 is a perspective view showing the wire connection state of different wiring boards for explaining the present invention, and FIGS. 2A and B and 3 A and B are steps showing an example of a conventional method for manufacturing a multilayer wiring board, respectively. 4A to 4E are process diagrams showing the manufacturing method of the present invention, and FIGS. 5A and 5B are sectional views showing an example of the separation process of the present invention. 31 is a rigid insulating substrate, 34 is a first layer wiring pattern, 35 is a first part, 36 is a second part,
38 is a perforation, 39 is a release layer, 43 is a second layer wiring pattern, and 44 is an opening.

Claims (1)

【特許請求の範囲】[Claims] 1 所要の配線パターンを施した第1の部分と、
該第1の部分と連結されてはいるが機械的力によ
り分離される如く形成された第2の部分からなる
基板の前記第2の部分に離型層を形成する工程
と、前記第1の部分及び前記第2の部分の少なく
とも上下の接続部及び電気部品接続部を除いて絶
縁樹脂層を印刷形成する工程と、前記絶縁樹脂層
上に導電箔層を被着する工程と、前記導電箔層に
少なくとも前記第1の部分に施された配線パター
ンに到る開口部を形成して接続する工程と、前記
第2の部分を前記第1の部分より機械的に分離す
る工程から成る多層配線基板の製法。
1. A first part with a required wiring pattern,
forming a release layer on the second part of the substrate, the second part being connected to the first part but separated by mechanical force; a step of printing an insulating resin layer except for at least the upper and lower connecting portions of the part and the second portion and the electrical component connecting portion; a step of depositing a conductive foil layer on the insulating resin layer; and a step of depositing a conductive foil layer on the insulating resin layer. A multilayer wiring comprising the steps of forming and connecting an opening in a layer to a wiring pattern formed on at least the first portion, and mechanically separating the second portion from the first portion. Substrate manufacturing method.
JP13532581A 1981-08-28 1981-08-28 Method of producing multilayer circuit board Granted JPS5835998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13532581A JPS5835998A (en) 1981-08-28 1981-08-28 Method of producing multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13532581A JPS5835998A (en) 1981-08-28 1981-08-28 Method of producing multilayer circuit board

Publications (2)

Publication Number Publication Date
JPS5835998A JPS5835998A (en) 1983-03-02
JPS6246080B2 true JPS6246080B2 (en) 1987-09-30

Family

ID=15149115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13532581A Granted JPS5835998A (en) 1981-08-28 1981-08-28 Method of producing multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS5835998A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158294A (en) * 1984-08-29 1986-03-25 シャープ株式会社 Method of producing printed circuit board
JP4503963B2 (en) * 2003-09-18 2010-07-14 株式会社山武 Sensor electrode extraction method
JP4492280B2 (en) * 2004-09-29 2010-06-30 日立電線株式会社 Electronic component mounting structure and optical transceiver using the same

Also Published As

Publication number Publication date
JPS5835998A (en) 1983-03-02

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