JPS624878B2 - - Google Patents
Info
- Publication number
- JPS624878B2 JPS624878B2 JP16058978A JP16058978A JPS624878B2 JP S624878 B2 JPS624878 B2 JP S624878B2 JP 16058978 A JP16058978 A JP 16058978A JP 16058978 A JP16058978 A JP 16058978A JP S624878 B2 JPS624878 B2 JP S624878B2
- Authority
- JP
- Japan
- Prior art keywords
- mixture
- circuit board
- metal
- copper
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 239000000843 powder Substances 0.000 description 12
- 239000010949 copper Substances 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000003973 paint Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 229910001338 liquidmetal Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 3
- 229910052753 mercury Inorganic materials 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229910017980 Ag—Sn Inorganic materials 0.000 description 1
- 229910000497 Amalgam Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 235000011837 pasties Nutrition 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004065 wastewater treatment Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、回路基板、特に複数の配線パターン
が積層され、各層の配線パターンが透孔を通して
導通されて成る所謂多層回路基板に係わる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit board, and particularly to a so-called multilayer circuit board in which a plurality of wiring patterns are stacked and the wiring patterns in each layer are electrically connected through through holes.
先づ、本発明の理解を容易にするために従来の
多層回路基板について説明しよう。第1図は従来
の多層回路基板の一例を工程順に示すもので、之
は先づ、同図A及びBで示すようにフエノール樹
脂、エポキシ樹脂等からなる絶縁基板1の上下両
面に夫々銅箔2,2′を被着して成る所謂銅張り
積層板3を設け、この積層板3の所要位置に上下
に貫通する透孔4を穿設し、次に透孔4の内側面
及び銅箔2,2′を含むように表面に化学メツキ
と電気メツキを順次施して銅メツキ層5を形成し
(同図C)、次に透孔4内にエツチングレジスト6
を埋め込むと共に銅箔2及び2′上に配線パター
ンに対応したパターンのエツチングレジスト7を
印刷形成し(同図D及びE)、次に、同図F及び
Gに示すようにレジスト6及び7をマスクとして
銅箔2及び2′を選択エツチングして夫々配線パ
ターン8及び8′を形成して後、レジスト6及び
7を除去して構成される。 First, in order to facilitate understanding of the present invention, a conventional multilayer circuit board will be explained. FIG. 1 shows an example of a conventional multilayer circuit board in the order of steps. First, as shown in A and B in the same figure, copper foils are placed on the upper and lower surfaces of an insulating substrate 1 made of phenol resin, epoxy resin, etc. A so-called copper-clad laminate 3 made of copper-clad laminates 2 and 2' is provided, and through-holes 4 that pass through the laminate 3 vertically are bored at desired positions, and then the inner surface of the through-hole 4 and the copper foil are A copper plating layer 5 is formed by sequentially applying chemical plating and electroplating to the surface so as to include 2 and 2' (FIG. C), and then an etching resist 6 is applied in the through hole 4.
At the same time, an etching resist 7 with a pattern corresponding to the wiring pattern is printed on the copper foils 2 and 2' (D and E in the same figure), and then resists 6 and 7 are etched as shown in F and G in the same figure. After selectively etching the copper foils 2 and 2' as masks to form wiring patterns 8 and 8', respectively, the resists 6 and 7 are removed.
第3図は従来の多層回路基板の他の例であり、
之は上記と同様の銅張り積層板3に対し、先に銅
箔2,2′を選択エツチングして配線パターン8
及び8′を形成し(同図A及びB)、次に所要の位
置にパターン8及び8′にわたる透孔4を穿設し
て後、銀ペイント9を透孔4内に充填し両配線パ
ターン8及び8′を電気的に接続して構成され
る。 Figure 3 shows another example of a conventional multilayer circuit board.
This is done by first selectively etching the copper foils 2 and 2' on the same copper-clad laminate 3 as above to form the wiring pattern 8.
and 8' (see A and B in the same figure), and then, after drilling a through hole 4 spanning patterns 8 and 8' at a required position, silver paint 9 is filled in the through hole 4, and both wiring patterns are formed. 8 and 8' are electrically connected.
然るに、このような第1図及び第3図で示す従
来の多層回路基板においては下記のような欠点が
あつた。例えば第1図の多層回路基板10では、
メツキを行うなど工程が複雑で歩留りが悪く、且
つその公害上の廃水処理も容易でないこと、銅メ
ツキ層5が全面メツキされ不要箇所の銅の析出が
無駄となること、さらに第2図で示すように銅メ
ツキ層5を形成して後の選択エツチングの際にア
ンダーカツト12により配線パターン8又は8′
が細りパターン精度が悪くなること、等の欠点が
あつた。又、第3図の多層回路基板11では、透
孔4に充填される銀ペイント9が樹脂や溶剤を多
量に含むために第4図で示すように硬化により体
積収縮が大きくなり銀粉の濃度を増しても抵抗値
に限度があり(10-4Ωcm)、また段切れが生じ易
いこと、さらに小径の透孔4への銀ペイント9の
充填がむずかしく高密度回路が作り難いこと、等
の欠点があつた。 However, the conventional multilayer circuit boards shown in FIGS. 1 and 3 have the following drawbacks. For example, in the multilayer circuit board 10 shown in FIG.
The process of plating is complicated and the yield is low, and the wastewater treatment due to pollution is not easy.The copper plating layer 5 is plated all over, and the copper deposits in unnecessary areas are wasted, as shown in Fig. 2. After forming the copper plating layer 5, the wiring pattern 8 or 8' is formed by the undercut 12 during selective etching.
There were drawbacks such as thinning and poor pattern accuracy. Furthermore, in the multilayer circuit board 11 shown in FIG. 3, the silver paint 9 filled into the through holes 4 contains a large amount of resin and solvent, so as shown in FIG. Disadvantages include that even if the resistance is increased, there is a limit to the resistance value (10 -4 Ωcm), breakage is likely to occur, and it is difficult to fill the small-diameter through hole 4 with silver paint 9, making it difficult to create a high-density circuit. It was hot.
本発明は、上述した従来の欠点を解消し、製造
容易にして信頼性の高い回路基板を提供するもの
である。 The present invention solves the above-mentioned conventional drawbacks and provides a circuit board that is easy to manufacture and has high reliability.
以下、第5図〜第7図を用いて本発明による回
路基板をその製法と共に説明しよう。 Hereinafter, the circuit board according to the present invention and its manufacturing method will be explained using FIGS. 5 to 7.
本発明においては、第5図Aに示すように例え
ばフエノール樹脂、エポキシ樹脂等からなる絶縁
基板1の上下両面に夫々銅箔2及び2′を被着し
てなる所謂銅張り積層板3を用意し、次に積層板
3の上下銅箔2及び2′を選択的にエツチングし
て夫々基板1の両面に所定の配線パターン8及び
8′を形成して後、基板1の所定位置に両配線パ
ターン8及び8′にわたる如く透孔4を形成する
(第5図B及びC)。然る後、この透孔4内に、下
記に詳述するペースト状の金属の混合物15を充
填し、この混合物15を合金固化して両配線パタ
ーン8及び8′を電気的に接続する導電体17を
形成し、第5図で示す目的の回路基板18を構成
する。 In the present invention, as shown in FIG. 5A, a so-called copper-clad laminate 3 is prepared by coating copper foils 2 and 2' on the upper and lower surfaces of an insulating substrate 1 made of, for example, phenolic resin, epoxy resin, etc. Next, the upper and lower copper foils 2 and 2' of the laminated board 3 are selectively etched to form predetermined wiring patterns 8 and 8' on both sides of the board 1, respectively. A through hole 4 is formed so as to span the patterns 8 and 8' (FIGS. 5B and 5C). After that, the through hole 4 is filled with a paste-like metal mixture 15, which will be described in detail below, and this mixture 15 is solidified as an alloy to form a conductor that electrically connects both wiring patterns 8 and 8'. 17 is formed to constitute the intended circuit board 18 shown in FIG.
混合物15は第6図A及びBに示すように常温
において液状の金属13と、この金属13と合金
を形成しうる金属粉末14(単体の金属粉末又は
合金粉末)を適量混合して成る。この混合物15
は当初ペースト状をなし、経時的に合金化し凝固
する。即ち第6図Cに示すように合金固体16と
なる。一般に凝固した合金をアマルガムと呼ぶ。
常温で液状の金属13としては水銀Hgが好適で
ある。又、金属13と合金化する金属粉末14、
従つて水銀と合金する金属粉末としては、例えば
単体金属では銀Ag、錫Sn、銅Cu、パラジウム
Pd、亜鉛Zn、インジウムIn、金Au、アルミニウ
ムAl等、合金ではAg−Sn−Cu、Ag−Sn、Cu−
Sn、Ag−Sn−Pb等を用い得、合金化された形態
はAg2Hg3、Sn7Hg、Cu2Hg3、その他等となる。
これらの金属粉末14の粒径は0.5μ〜200μの範
囲が好ましい。液状の金属13と金属粉末14の
配合比は、液状の金属13:金属粉末14が30:
70〜70:30(重量%)の範囲が好ましい。金属粉
末が70重量%を超えた場合にはその混合物15が
ペースト状とならず、又30重量%より少ないと液
状の金属13、この例では水銀Hgが残留して完
全に固化しない。一方、第5図Cの工程後、透孔
4内へのかかる混合物15の充填は、第7図に示
すように、基台19上にパターン8,8′及び透
孔4が設けられた基板1を配し、スキージ20に
よつて混合物15を充填して行く。なお水銀Hg
と上記金属粉末14とを1〜2分混合すると可塑
性のあるペースト状の混合物15が得られ、この
混合物は充填して室温で1日後合金化し固化す
る。充填に際して、混合物15は表面張力により
基板1の表面に付着されず、透孔4内のみに充填
されるために基板表面を汚すことがない。又、小
径の透孔4への充填も容易になし得る。 As shown in FIGS. 6A and 6B, the mixture 15 is made by mixing an appropriate amount of a metal 13 that is liquid at room temperature and a metal powder 14 (single metal powder or alloy powder) that can form an alloy with the metal 13. This mixture 15
initially forms a paste, and over time it alloys and solidifies. That is, it becomes an alloy solid 16 as shown in FIG. 6C. The solidified alloy is generally called an amalgam.
Mercury Hg is suitable as the metal 13 which is liquid at room temperature. Also, a metal powder 14 alloyed with the metal 13,
Therefore, metal powders that can be alloyed with mercury include, for example, silver Ag, tin Sn, copper Cu, and palladium.
Pd, zinc Zn, indium In, gold Au, aluminum Al, etc., and alloys such as Ag-Sn-Cu, Ag-Sn, Cu-
Sn, Ag- Sn -Pb, etc. can be used, and the alloyed form is Ag2Hg3 , Sn7Hg , Cu2Hg3 , etc.
The particle size of these metal powders 14 is preferably in the range of 0.5μ to 200μ. The mixing ratio of liquid metal 13 and metal powder 14 is 30: liquid metal 13:metal powder 14.
A range of 70 to 70:30 (wt%) is preferred. If the metal powder exceeds 70% by weight, the mixture 15 will not become pasty, and if it is less than 30% by weight, the liquid metal 13, in this example mercury Hg, will remain and will not solidify completely. On the other hand, after the process shown in FIG. 5C, the through holes 4 are filled with the mixture 15, as shown in FIG. 1 and fill it with the mixture 15 using a squeegee 20. Furthermore, mercury Hg
By mixing the metal powder 14 and the metal powder 14 for 1 to 2 minutes, a plastic paste-like mixture 15 is obtained, and this mixture is filled and alloyed and solidified at room temperature for one day. During filling, the mixture 15 is not attached to the surface of the substrate 1 due to surface tension and is filled only into the through holes 4, so that the surface of the substrate is not contaminated. Furthermore, small-diameter through holes 4 can be easily filled.
尚、第5図では両面に配線パターン8,8′を
有した2層回路基板に適用したが、第8図で示す
ように配線パターン8を4層に設けた回路基板
等、所謂多層回路基板にも本発明を適用できるこ
と勿論である。 In addition, in FIG. 5, the application is applied to a two-layer circuit board having wiring patterns 8 and 8' on both sides, but as shown in FIG. Of course, the present invention can also be applied to
上述せる本発明によれば、室温でペースト状を
なし経時的に合金化し固化する性質を有する全て
金属で構成せる混合物15を透孔4内に充填する
ことにより、充填後の導電体17の体積収縮がな
く、透孔4内の導電体17の抵抗も金属のもつ固
有抵抗で決まり、優れた値いを示す。例えば厚さ
1.6mm、直径0.5mmの透孔4内の導体抵抗を従来と
比較すると、銅メツキ(第1図の場合)では0.35
mΩ、銀ペイント(第3図の場合)では500m
Ω、本発明(Ag−Sn−Hg)では0.9mΩとな
り、本発明がすぐれていることが認められる。 According to the present invention described above, the volume of the conductor 17 after filling is reduced by filling the through hole 4 with the mixture 15 made entirely of metals, which is paste-like at room temperature and has the property of alloying and solidifying over time. There is no shrinkage, and the resistance of the conductor 17 in the through hole 4 is determined by the specific resistance of the metal, and exhibits an excellent value. For example, thickness
Comparing the conductor resistance in the through hole 4 with a diameter of 1.6 mm and 0.5 mm, it is 0.35 with copper plating (in the case of Figure 1).
mΩ, 500m for silver paint (in the case of Figure 3)
Ω, in the present invention (Ag-Sn-Hg), was 0.9 mΩ, and it is recognized that the present invention is superior.
又、製造に際しては銀ペイントで導通をとる第
3図の場合と同様の工程でよく、且つ混合物の充
填も容易であるので、製造工程が簡素化される。
さらに小径の透孔4にも混合物15の充填が容易
であるので高密度配線も容易にでき、依つて信頼
性の高い回路基板を提供することができる。 In addition, the manufacturing process is simplified because the same process as in the case of FIG. 3, in which electrical conduction is achieved using silver paint, is sufficient, and filling with the mixture is also easy.
Further, since it is easy to fill the mixture 15 into the small-diameter through-holes 4, high-density wiring can be easily achieved, and a highly reliable circuit board can be provided.
第1図A〜Gは従来の多層回路基板の一例を示
す工程順の断面図、第2図はその要部の断面図、
第3図は従来の多層回路基板の他の例を示す工程
順の断面図、第4図はその要部の断面図、第5図
は本発明の回路基板の例を示す工程順の断面図、
第6図A〜Cは本発明で適用する混合物の形態を
示す図、第7図は混合物の充填方法の一例を示す
断面図、第8図は本発明の回路基板の他の例を示
す断面図である。
1は絶縁基板、4は透孔、8,8′は配線パタ
ーン、13は常温において液状の金属、14は他
の金属粉末、15は混合物、17は導電体であ
る。
FIGS. 1A to 1G are cross-sectional views showing an example of a conventional multilayer circuit board in the order of steps; FIG. 2 is a cross-sectional view of its main parts;
FIG. 3 is a sectional view showing another example of a conventional multilayer circuit board in the order of steps, FIG. 4 is a sectional view of its main parts, and FIG. 5 is a sectional view in order of steps showing an example of the circuit board of the present invention. ,
6A to 6C are diagrams showing the form of the mixture applied in the present invention, FIG. 7 is a cross-sectional view showing an example of a method of filling the mixture, and FIG. 8 is a cross-sectional view showing another example of the circuit board of the present invention. It is a diagram. 1 is an insulating substrate, 4 is a through hole, 8 and 8' are wiring patterns, 13 is a metal that is liquid at room temperature, 14 is another metal powder, 15 is a mixture, and 17 is a conductor.
Claims (1)
第2の配線と、該第1及び第2の配線にわたつて
上記基板に形成された透孔と、該透孔に充填され
上記第1及び第2の配線を電気的に接続する導電
体より成り、該導電体は常温で液状の第1の金属
と他の金属との合金より成ることを特徴とする回
路基板。1 first and second wiring formed through an insulated substrate, a through hole formed in the substrate across the first and second wiring, and a through hole filled with the first wiring. and a conductor that electrically connects the second wiring, the conductor being made of an alloy of a first metal and another metal that is liquid at room temperature.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16058978A JPS5586198A (en) | 1978-12-23 | 1978-12-23 | Circuit board and method of fabricating same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16058978A JPS5586198A (en) | 1978-12-23 | 1978-12-23 | Circuit board and method of fabricating same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5586198A JPS5586198A (en) | 1980-06-28 |
JPS624878B2 true JPS624878B2 (en) | 1987-02-02 |
Family
ID=15718215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16058978A Granted JPS5586198A (en) | 1978-12-23 | 1978-12-23 | Circuit board and method of fabricating same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5586198A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59119790A (en) * | 1982-12-24 | 1984-07-11 | 松下電器産業株式会社 | Multilayer printed circuit board and method of producing same |
JPH0724334B2 (en) * | 1987-01-19 | 1995-03-15 | 株式会社日立製作所 | Circuit board |
JP4819608B2 (en) * | 2006-07-31 | 2011-11-24 | 富士フイルム株式会社 | Liquid ejection head, liquid ejection apparatus, and image forming apparatus |
-
1978
- 1978-12-23 JP JP16058978A patent/JPS5586198A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5586198A (en) | 1980-06-28 |
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