JPS6243572B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention continuously compares the digital value contained in a numerical register with the contents of a counter fed with a count pulse train, starting from the initial state of the counter until both values become equal. A method of digital-to-analog conversion, in which at least one group of bit outputs of a counter is compared with bit outputs of a memory of a different order in order to determine the duty ratio of the pulse signal and to increase the frequency of the pulse signal. It relates to a device for. This type of digital-to-analog converter was published in the article "Digital-to-analog converter capable of MOS integration" in the magazine "FUNK.TECHNIK (Radio Technology)" Vol. 30, No. 7, 1975, pages 180 to 184.
It is described in. One of the pulse width modulation circuits shown in this paper includes a digital value register and
It has a counter and a comparator fed with a digital value register and the bit output of the counter.
The counter is continuously clocked by the oscillator's output pulse train. The instantaneous state of the counter is fed to one input A of the comparator. The other input B of the comparator is connected to the bit output of the register containing the digital value to be converted.
This comparator is configured to emit a square wave signal if A<B. The pulse width of this signal is proportional to the digital value at input B of the comparator. This signal is related to a reference voltage and can be extracted via a reduction filter. The fundamental wave is obtained by dividing the pulse train frequency of the oscillator by the count range of the counter, and a low-pass filter must be designed for this fundamental wave.

Another circuit described in the same paper similarly includes counters, registers and comparators. However, in this circuit, all the bit outputs of the counter are cross-connected to the corresponding inputs of the comparator, such that the least significant bit of the counter is tied to the most significant bit of the comparator, and vice versa. ing. This circuit operates in a manner referred to in the same paper as the stochastic method. At the output end of the comparator,
No signal with a uniform frequency is produced. Since the average output signal frequency is higher than that of the previously listed circuits, faster conversion can be achieved and the cost for low pass filters can be saved. However, the article
The disadvantages of the stochastic method are also listed at the bottom of the right column on page 181 and at the bottom of the left column on page 182.

German Patent Application No. 2317851 describes the method mentioned at the outset. In column 4, lines 50 to 56 of this publication, it is stated that the effect of increasing the frequency of the output signal of the converter is not independent of the magnitude of the digital value to be converted. At the center of the conversion range the frequency increase factor is maximum. The frequency increase coefficient decreases linearly to 1 as the ends of the conversion range are approached.

The object of the invention is to improve a method of the type described at the outset in such a way that the frequency rise factor does not decrease from its highest value closer to the ends of the conversion range, but remains constant in magnitude up to the ends. .

This purpose, according to the invention, is such that all the bit outputs of the counter are shifted by a predetermined number of bits in the direction of increasing digits toward the register with respect to the bit output of the register to be compared; The bit output at the most significant end of the counter is opposite the bit output at the least significant end of the register by a predetermined number, and the bit following the least significant bit of the register is opposite the bit output at the least significant end of the register. This is achieved by a digital-to-analog conversion method characterized in that one increment is added each time the present value exceeds the instantaneous content of the most significant bit of the counter with which it is compared.

The advantage of the method according to the invention compared to the method described in said publication is that the output signal has a frequency that is independent of the magnitude of the digital value to be converted. Thereby, the number of openings and closings required to represent one bit of the digital value can be estimated.
It is possible to predict how the temperature effects of the rise and fall of the output signal affect the accuracy of the conversion, thus allowing its compensation.

A digital-to-analog conversion device for carrying out the method of the present invention has the lowest bit output terminal of the register and the highest bit output terminal of the counter connected to the comparison input terminal of a digital numerical comparator. The output terminal of the comparator that determines "counter value is less than the register value" is connected to the transmission input terminal of the adder, and the first addend bit input terminal of this adder is connected to the upper bit output terminal of the register. Also, its second addend bit input terminal is connected to zero potential, the sum bit output terminal of this adder is connected to the bit input terminal of a subtraction counter, and the set signal input terminal of this subtraction counter is connected to the transmission output of the bit preceding the most significant bit of the counter, and the count input of this subtraction counter receives the same count pulse that is giving the count pulse to the above counter via an AND gate. The second input of this AND gate is connected to the transmission output of the subtraction counter via an inverter, and the pulse width modulated signal of the digital-to-analog converter is connected to the transmission output of the digital-to-analog converter. It is expedient to arrange the output signal in such a way that it appears.

Other digital-to-analog converters which are also suitable for carrying out the method according to the invention include a comparison bit input connected on the one hand to the bit output of a register for the digital value to be converted, and on the other hand a counting pulse generator. a comparator connected to a bit output terminal of a counter to which a pulse train of In a digital-to-analog converter in which the pulse width modulated signal can be extracted from the output of the comparator, the output of the count pulse generator is connected to the count input of the bit following the least significant bit of the counter. The count input of the least significant bit of the counter is connected to the transmission output of the most significant bit of the counter, and the least significant bit of the comparator is connected to the transmission output of the most significant bit of the counter. The output terminal of the bit is connected to the input terminal of the bit next to the least significant bit of the comparator, which is originally prepared for the signal indicating that the counter state is equal to the contents of the respective register. It is expedient that the device is configured to emit an output signal when the counter state is equal to or less than the respective register content.

Registers and counters may be organized according to pure binary or mixed number systems. Ten
According to the base number system, the system power of 10 is obtained as the output signal frequency increase coefficient. Advantageously, the selection of the coefficients is adapted to the frequency response characteristics of the low-pass filter utilized.

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, three digits of counter Z are shown opposite three digits of register Sp. The count input terminal of the least significant digit of the counter Z is connected to the output terminal of the count pulse generator TG. The transmission output terminals of the lower digits are respectively connected to the count input terminals of the upper digits. Counter Z
The bit output terminal of the most significant digit is connected to the comparison input terminal A of the comparator HK. The equivalent bit input B of the comparator HK is connected to the least significant bit output of the register Sp. The bit output terminals of the digits following the least significant digit of the register Sp are connected to the input terminals C of adders Add1 and Add2, which are also arranged for each digit. Addition input terminal D of adder
is connected to zero potential. Adder Add1 and
The addition bit output terminal Σ of Add2 is the subtraction counter RZ
are connected to the bit inputs of the two corresponding digits. The transmission input of the adder Add1 is connected to the decision output of the comparator HK, and the value stored in the most significant digit of the counter Z is smaller than the value stored in the least significant digit of the register Sp. sometimes,
A signal is emitted from the decision output terminal. Adder Add1
The transmission output terminal of is connected to the transmission input terminal of adder Add2. The count input of the subtraction counter RZ is connected via an AND gate G to the output of the timing pulse generator TG. The second input terminal of the AND gate G is connected via an inverter I to the transmission output terminal of the most significant digit of the subtraction counter RZ. A low-pass filter T is also connected to this output terminal, from which an analog value can be extracted. The transmission output terminals of the digits located between the least significant digit and the most significant digit of the counter Z are connected to the set input terminals of both digits of the subtraction counter RZ.

The manner in which this digital-to-analog converter operates will be explained below. The digits of counter Z, which counts continuously, are compared to the digits of register Sp.
It is shifted by one digit in the direction of increasing digits on the register side. At that time, the most significant digit of counter Z is the comparator.
It faces the least significant digit of register Sp via HK. If the counter state of the most significant digit of the counter is less than the contents of the least significant digit of register Sp, then
Comparator HK provides the transmission signal to adder Add1.
This adder adds one increment to the value being applied to its addend bit input C. The subtraction counter is set to the above-mentioned corrected sum value each time counter Z applies a transmission pulse to a digit located between the most significant and least significant digit. The subtraction counter RZ counts down from this value at a frequency equal to the frequency at which the counter Z performs up-counting and down-counting, and stops when the content reaches zero. The subtraction counter then continues to emit an output signal until it is again loaded with the sum value from the adders Add1 and Add2.

In FIG. 2, the three digits of the counter 2 are connected on the output side to the comparison inputs A of the three digits of the corresponding comparator K. The other comparison input B of the comparator K is connected to the three-digit bit output of the register Sp. A low-pass filter T is connected to the output terminal of the most significant digit of the comparator K (criterion A≦B). The output of the count pulse generator TG is connected to the second digit count input of the counter Z. The count input terminal of the first digit of counter Z is connected to the transmission output terminal of the most significant digit of counter Z. The output of the first digit of comparator K (criterion A<B) is connected to the transmission input of the second digit of comparator K (criterion A=B). The transmission output of the second digit of comparator K (criteria A<B, A=B and A>B)
It is connected to the transmission input terminal corresponding to the most significant digit.

In FIG. 3, the output signal of comparator K is shown as a discrete logic value that is related to the comparator's least significant digit decision criterion and its most significant digit decision criterion.
The left column of the diagram contains the decision criteria for the least significant digit, the center column the decision criteria for the most significant digit, and the right column the output signals as logical “1” and logical “0”. It is filled in.

FIG. 4 shows the time course of the output signal of the comparator K for the ten run units 0 to 9 of the least significant digit of the counter Z. At this time, it is assumed that the register content of the least significant digit is 3. As can be seen from the figure, among the 10 run states, the 3 included in the least significant digit of the counter is equal to the 3 additional digits in the first three run states in the output voltage.
Represented as the 10th bit. Furthermore, as can be seen from the figure, the output signal of comparator K becomes zero for A=B in the least significant digit. This is because the transmission input of the digit following the least significant digit is no longer driven. The example shown in FIG. 4 concerns a comparator K operating in decimal notation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a digital-to-analog converter for carrying out the method according to the invention, and FIG. 2 shows a second embodiment of a digital-to-analog converter for carrying out the method according to the invention. An example block circuit diagram, FIG. 3 is a diagram showing the relationship between the output signal of the comparator of the digital-to-analog converter of FIG. FIG. 4 shows the time course of the output signal of the comparator of the digital-to-analog converter of FIG. 2 for specific register contents. Add...adder, G...and gate, HK...
...Comparator, I...Inverter, K...Comparator,
RZ...Subtraction counter, Sp...Register, T...
Low-pass filter, TG...timing pulse generator, Z...counter.

Claims (1)

[Claims] 1. The digital value contained in the register is constantly compared with the contents of a counter to which a count pulse train is applied, and the time elapsed from the initial state of the counter until both values become equal is determined by the pulse signal. In a digital-to-analog conversion method, at least one group of bit outputs of a counter is compared with bit outputs of registers of different digits to determine the duty ratio and to increase the frequency of the pulse signal.
All bit outputs of the counter are shifted by a predetermined number of bits in the direction of increasing registers with respect to the bit outputs of the registers with which they are compared, such that the bit outputs at the most significant end of the counter is a predetermined number of bits opposite the bit output at the least significant end of the register, and the bits following the least significant bit of the register are of a counter with which the value appearing at the least significant bit output of the register is compared. A digital-to-analog conversion method characterized in that one increment is added each time as long as the instantaneous content of the most significant bit is exceeded. 2. The least significant bit output of the register for the digital value to be converted and the most significant bit output of the counter, which is continuously fed with a count pulse train, are connected to the comparison input of a digital numerical comparator. , the output terminal of the comparator that determines "counter value is smaller than the register value" is connected to the transmission input terminal of the adder, and the first addend bit input terminal of this adder is connected to the upper bit of the register. The output terminal and its second addend bit input terminal are connected to zero potential, and the sum bit output terminal of this adder is connected to the bit input terminal of a subtraction counter, and the set signal input of this subtraction counter The count input of this subtracting counter is connected to the transmission output of the bit preceding the most significant bit of the counter, and the count input of this subtraction counter is connected to the same count pulse that is giving the count pulse to said counter via an AND gate. The second input of this AND gate is connected to the transmission output of the subtraction counter via an inverter, and the pulse width modulated signal of the digital-to-analog converter is connected to the transmission output of the digital-to-analog converter. A digital-to-analog conversion device characterized in that an output signal appears. 3 a comparator whose comparison bit input is connected on the one hand to the bit output of a register for the digital value to be converted and on the other hand to the bit output of a counter fed with the pulse train of a counting pulse generator; , at least one group of the bit output terminals of the counter corresponds to the bit output terminals of the register whose digits do not match each other via a comparator, and a pulse width modulated signal can be taken out from the output terminal of the comparator, and the count The output end of the pulse generator is connected to the count input end of the bit following the least significant bit of the counter, and the count input end of the least significant bit of the counter is connected to the transmission output end of the most significant bit of the counter. The output terminal of the least significant bit of the comparator which emits a signal when is smaller than the contents of the respective register is the output terminal of the comparator which is originally prepared for the signal indicating that the counter state and the contents of the respective register are equal. Digital-to-analog conversion, characterized in that the comparator is connected to the input of the bit following the least significant bit and that the comparator provides an output signal when the counter state is equal to or less than the respective register contents. Device.