SU1254576A1 - Frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and provides the ability to control the phase of the output signal. The reference frequency d is related to the desired output frequency fg by the ratio fg. b (d fg). The numbers a, b, g (g capacity of accumulating adder (NS) 4) go to block 7 for dividing the codes, forming the whole Xd and fractional dX of the fraction, ag / b. Tsela and fractional parts come to acc. NA 4.3, which form a single NA. Code x (t) with HC 4 slope The sign is given in the adder of codes (CK) 8 with the modulating function (t), which is chosen so that the overflow pulse p (t) is formed at each cycle of the process x (t). The shift of the overflow moment of the SC 8 is proportional to the change in the number y. The signal from the IC 8 passes to the multiplexer 6 directly and through the block of elements NOT 9. The multiplexer 6 is controlled by pulses generated by the trigger 5, which is switched by the overflow pulses of the IC 8. Switch 10 can change the polarity of the control pulses. The signals from multiplexer 6 through the DAC 1 and filter 2 are output. The frequency synthesizer can be used in the mode of multipositional phase telegraphy and in the phase modulation mode, in which the modulating function 1Д1Я (р (t) provides a change in the phase of the output signal. A CK 8, a block of elements HE 9 and a switch 10. 1 or $ s (L y y (t) Щ Щ) & g (t)

Description

The invention relates to radio engineering and can be used in transceiver and measuring equipment.

The purpose of the invention is to enable control of the phase of the output signal.

The drawing shows an electrical structural diagram of a frequency synthesizer.

The frequency synthesizer contains a digital-to-analog converter (D / A converter) 1, filter 2, first accumulative summtor (HC) 3, second HC 4, trigger 5, multiplexer 6, block 7 of code division, adder 8 codes, block of elements HE 9, switch 10 .

The frequency synthesizer works as follows.

The division unit 7 produces the whole X (partial) and fractional Dx (residual) parts of the fraction ag / b, where g is the capacity of the second HC 4, filled as n - bit binary adder, and the numbers a and b are related to the reference d and the required output fg frequencies by the ratio fg fd x xa / 2b. The code inputs of the division block 7 receive the corresponding values of the dividend and the divisor. The latter is also used to control the capacity of the first HC 3, which converts the remainder q X into an overflow pulse p (t), which occurs when an entire unit is accumulated and is transmitted to the transfer input of the second HC 4. Both accumulators thus play the role of a single accumulator adder, the input number of which is equal to XD + dx / b,

The forward x (t) code from the output of the second HC4 is fed to the first input of the accumulator 8. In the last step, the digital function x (t) is summed with the modulating function (/ (t). The values of fy are chosen from the condition

g - (х „+1) (Хд,

where g 2 is the total capacity of the adder 8, made in the form of an n-bit binary adder, whereby an overflow pulse p (t) at the corresponding output of the adder 8 is formed at each cycle of the process x (t). If the voltage fails, the adder may either not overflow or be permanently full, due to which the operation of the device

disrupts. Considering that x, 1, and, therefore, Xd x ag / b, the constraints for y take the form

g - ag / b (ag / b (1) The offset of the moment of overflow of the adder B is proportional to the change in the number (p. As a result, the output of the adder 8 is formed by the functions (t), transmitted further to one of the multiplexer 6 inputs. To the other multiplexer input receives the function X, (t), obtained using a block of elements NOT 9. The multiplexer is controlled by pulses g (t) generated by trigger 5 with a counting input. The trigger is switched by the action of overflow pulses p (t) of the adder 8. The polarity of pulses g ( t) can be changed using switch 10, for which the inputs the latter is connected to the direct and inverse outputs of trigger 5, and the control input is connected to the bus Sign to which the corresponding logic level is applied.

As a result of switching the trigger 5 to the output of the multiplexer 6, the functions X, (t) and x (t) are alternately transformed further by means of the DAC 1 to analogue equivalents. In this way, the numerical g (t) and the corresponding analogue G (t) functions are formed, representing an alternation of the ascending and descending sections, so matching with each other, that the average value, which is higher than the filter 2, is periodic function with frequency fg ffl a / 2b, High-frequency sawtooth component Gd (t), the spectrum of which is concentrated near the reference frequency f is easily suppressed by filter 2, because in practice fd fj, It is also easy to select the first harmonic of the signal Gg (t), if the upper frequency f of the cutoff of filter 2 is chosen from 3f catch 7 (the second and other even harmonics Gg (t) no signal).

Filter 2 can be either in the form of a band pass or in the form of a low-pass filter. As the switch 10, a one-bit multiplexer can be used.

The magnitude of the phase shift of the sawtooth step function x (t) (as noted above) depends on the increment c (f of the modulating digital signal ((t) and is equal to ACf, 2 2 iT u (fV. Phase shift of the output signal G (j (t) two times less (due to doubling the period) and equal to lCf UV / I PR changes (within the limits of g the output signal phase increases in radians. Since the polarity of the function Gg (t) can be set by applying the appropriate logic level to the bus The sign, the phase control limits, extend to a full period, i.e..

When using a frequency synthesizer in the mode of multipositional phase telegraphy, the above restrictions on the numerical values of the code (f in (1) determine the maximum number of positions that should not exceed

iafcg 0 /

(2)

The first (senior) bit is manipulated at the second input of the adder 8 and the pin. The character provides 4-position phase telegraphy with a phase change discreteness. Adding a second bit for manipulation increases the number of positions to eight, etc. At the same time, in the bit following the youngest bit from among those involved in the manipulation, one should be set, and in the following bits - the zeros that are necessary to fulfill the condition (1 Taking into account, moreover, condition (2) is necessary so that the number of code bits (f involved in the manipulation does not exceed

Mavc ° g j / iax i

(3)

As a rule, the required number of positions is several units, and the constraints (2) and (3) are not rigid.

When using the invention in the phase modulation mode, when the tf code approximates the corresponding analog process and is normalized with respect to the required modulation index, the highest bit of the code is set to one or some of the remaining (minor) bits (depending on the required modulus index). Signs and Bus Sign are used to obtain phase modulation. Maximum achievable deviation

the phases in this case (when all the bits except the elder are involved) are as follows from (1),

Aq)

Max

 K / 2- -a / b).

ten

ts

20

25

thirty

35

40

45

0

five

The frequency synthesizer provides | almost unerringly control of the signal phase with high accuracy determined by the resolution of DAL 1. With a 10-bit PDP 1, for example, the error does not exceed ± n / 2. 0.003 happy 0.2.

Claims (1)

Invention Formula A frequency synthesizer containing a serially-connected multiplexer, a digital-to-analog converter and a filter, a serially connected code division unit, a first accumulating adder and a second accumulating adder, and a trigger, a code input of the second accumulating adder, and a second code input of the first accumulator the adder is combined with the first code input of a code division block and is an input of a frequency synthesizer divider; the second code input of a division block the codes is the input of the frequency synthesizer to be divided, the clock input of the code division unit is combined with the clock inputs of the first and second accumulating adders and is the reference input of the frequency synthesizer, which, in order to control the phase of the output signal, between the output of the second accumulating adder and the first multiplexer code input are entered in series connected adder codes and a block of elements NOT and also a switch is introduced, the output of which is connected to the control input of the multiplexer The typelexer, the second code input of which is connected to the output of the code adder, the overflow output of which is connected to the trigger input, the direct and inverse outputs of which are connected respectively to the first and second inputs of the switch, while the control input of the switch and. the second input of the adder codes are respectively the input control of the sign and the input control the magnitude of the phase shift of the frequency synthesizer.