JPS593704B2 - Period comparison circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that digitally compares the periods of signals.

To compare periods, the comparison result can be obtained by gating a clock-driven counter with an input signal.

However, such a method requires a counter dedicated to this purpose, and furthermore, in order to compare with a reference period, a delay circuit is required to obtain a fixed time delay corresponding to the size of the reference period. In order to configure the delay circuit digitally, it is necessary to change the length of the shift register or the feedback of the counter depending on the size of the reference period.

There is also a method of changing the clock frequency, but if a crystal oscillation circuit or the like is used to obtain a stable frequency, it is not easy to change the clock frequency. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the above-mentioned prior art and to provide a period comparator circuit which has a simple structure and is suitable for use for many purposes.

The main point of the present invention is that when the comparison input u() comes in, 10
The reference period is calculated by importing the current clock data xl() into the first register and adding the clock data xl() and the clock data increment a corresponding to the reference period using an adder/subtractor. The clock data X2 (+1) is calculated and stored in the second register.

Then, take in the clock data xl (+1) when the next comparison input u (+1) is input into the first register, and use the adder/subtractor to convert the clock data xl (+1) to the above. X2(
Perform period comparison by subtracting +1) and
The comparison result is y(+1). 20 In other words, by calculating x2 (+1) xl (+1) xl (+1) xl (+1) - x2 (+1) using an adder/subtractor, the positive and negative period comparison results with respect to the reference period are obtained. can be obtained.

25 The present invention will be specifically explained with reference to an embodiment shown in FIG.

When comparison input u comes into input terminal 5, input terminal 1
The clock data which is the output of the counter 2 driven by the clock pulse from the first register 3 is taken into the first register 3.

Here, the counter 2 can be selected to have an appropriate size N so as to obtain a period larger than the period of the input signal whose period is to be compared. The base of the counter 2 only needs to be the same as the base used by the adder/subtractor T, and any base suitable for handling periodic comparison data such as binary or decimal may be used. Then, using the contents of the second register 4 as clock data of the reference period, the values of the first register 3 and the second register 4 are subtracted by an adder/subtractor 7 modulo a value N, which is the same as the size of the counter 2. , 3rd
The period comparison result y is inputted into the register 8 of.

Then, the adder/subtractor 7 adds the first register 3 and the increment a of the clock data with respect to the reference cycle, which is the content of the memory 6, to calculate the reference cycle clock data for the next cycle comparison input. store. In order to treat the cycle comparison result y as a digital quantity, it is sufficient to output the contents of the register 8. Furthermore, in order to obtain the pulse width density modulation signal z in order to obtain an analog quantity proportional to the period comparison result y, the counter 2
can be easily obtained by gating the clock data which is the output of , using the period comparison result y.

FIG. 2 is an example of the gate circuit 9, with a circuit at A,
Figure B shows its operating waveform. The figure shows a case where the clock data is divided into four pits. Phase comparison data y: QA, QB, QC, QD from the register 8 is input to the terminal group 11 . QA is the lowest rank and QD is the highest rank. Terminal group 1
Clock data 0A, 0B, 0C, and 0D are input to 2. 0A is the lowest rank and 0D is the highest rank.

Each digit QA, QB, QC, QD of phase comparison data y
are gated by the clock data passed through the inverter group 13 in the AND gate group 14, and their output is 0R.
A pulse width density modulated pulse signal z, which is collected at a gate 15 and corresponds to the phase comparison data y, is obtained at a terminal 10. Figure b
3 shows waveforms of pulse width density modulation pulses z for several cases of phase comparison data y. In the figure, a indicates clock data, and B, c, d, and e indicate that each digit of phase comparison data y is QDQCQB''QA,''QDQCOBσA, σDηC.
QBQA,'QDOC'Q. The waveform of the pulse width density modulation pulse z in each case of BQA is shown. As described above, according to the present invention, comparison with the reference period does not require a delay circuit corresponding to the size of the reference period, nor does it require a dedicated counter.

By changing the contents of the memory 6, it can be easily applied to many purposes.

Therefore, even if integrated circuits are planned, the contents of the memory 6 can be easily changed by changing one mask, etc.
It is also suitable for integrated circuits and has a wide range of applications. Furthermore, memory 6
By storing a plurality of constants in the memory, it is possible to use them for different reference periods by switching memory addresses or the like.

Furthermore, when comparing a plurality of periods at the same time, the same counter can be used and the circuit can be simplified.

Furthermore, in many cases, the period of the signal for period comparison is sufficiently large compared to the addition/subtraction time, and the adder/subtractor can be shared in a time-division manner without causing problems due to delay.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
This figure is a diagram showing an example of a gate circuit for obtaining a pulse width density modulation signal in the embodiment of FIG. 1. 1...Clock input signal, 2...Counter, 3...First register, 4...
Second register, 5... Comparison signal input terminal, 6
...Memory, 7...Adder/subtractor, 8...
...Third register, 9...Gate circuit,
10...Output terminal.

Claims (1)

[Claims] 1. A counter driven by a clock signal, a first register that captures clock data that is the output of the counter when a comparison input signal is input, and a second register that stores clock data of a reference period. , an adder/subtracter for calculating the difference between the data in the first and second registers, a third register for storing the period comparison result which is the output of the adder/subtractor, and a third register corresponding to one period of clock data of the reference period. 1. A cycle comparison circuit comprising: a memory for storing a constant; the contents of the memory and the contents of the first register are added by the adder/subtractor and the result is stored in the second register.