CH646823A5 - Method of converting a digital value into an analog value, and digital-analog converter to implement the method - Google Patents

Description

The invention relates to a method for converting a digital value into an analog value, in which the digital value contained in a number memory is continuously compared with the content of a counter loaded by a counting pulse sequence and the time elapsing from an initial state of the counter until the two numerical values become equal determines the pulse duty factor of a pulse signal and in which, in order to increase the frequency of the pulse signal, at least one group of bit outputs of the counter is compared with bit outputs of the memory which do not correspond in terms of value, and on a digital-to-analog converter for carrying out the method.

Digital-to-analog converters are described in the article “MOS-integrable digital-to-analog converters” in the magazine “Funk-Technik”, 30th year, No. 7/1975, pages 180 to 184. One of the pulse width modulation circuits specified in the article has a digital value memory, a counter and a comparator loaded with bit outputs of the aforementioned units. The counter is continuously counted by the output pulse train of an oscillator. Its current status is at one input A of the comparator. The bit outputs of the memory, which contains the digital value to be converted, are connected to the other input B of the comparator. The comparator is set up in such a way that it supplies a square-wave signal when A <B. The pulse width of this signal is proportional to the digital value at input B of the comparator. It can refer to a reference voltage and be averaged over a low pass. The pulse repetition frequency of the oscillator, divided by the counting range of the counter, gives the fundamental wave for which the low-pass filter must be designed.

Another circuit described in the article also has counters, memories and comparators. However, all bit outputs of the counter are cross-connected to the corresponding inputs of the comparator in such a way that the least significant bit of the counter is located on the most significant bit of the comparator and vice versa. This circuit works according to the so-called stochastic method in the article. There is no signal with a uniform frequency at the output of the comparator. The average output signal frequency is higher than in the circuit described above, so that a faster conversion can be achieved and the effort for the low pass can be saved. On page 181 ', in the right column below, and page 182, left column above, disadvantages of the stochastic method are also listed.

The German method of writing 23 17 851 shows the procedure described in the introduction. In the fourth column, lines 50 to 56, the design specification mentions that the desired effect of increasing the frequency of the output signal of the converter is not independent of the size of the digital value to be converted. The frequency increase factor is greatest in the middle of the conversion range. Towards the two edge areas it drops linearly down to the value 1.

The invention has for its object to modify a method of the type described in such a way that the

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Frequency increase factor does not drop from a maximum value to both edge areas, but remains the same up to the limits of the area.

According to the invention, this goal is achieved in that all the bit outputs of the counter are shifted by a predetermined number of bits in relation to the bit outputs of the memory to be compared in the direction of the position value increasing on the memory side, with bit outputs of the counter at the end having the highest value bit outputs of the memory at its end The lowest number of positions in the specified number, and that an increment is added to the bits following the bits with the lowest position value in the memory, as long as the number value at the bit outputs with the lowest position value in the memory compares the current content of the bits with the highest position value of the counter compared with it surpasses.

The advantage achieved by the invention compared to the method that can be derived from the interpretation is that the output signal has a frequency that is independent of the size of the digital value to be converted. As a result, the number of switching cycles that are necessary to map a bit of the digital value can be overlooked. The temperature influence of the switching edges on the accuracy of the implementation can be estimated and therefore compensated.

A digital-to-analog converter for carrying out the method is expediently set up in such a way that the bit outputs with the lowest position value of the memory and the bit outputs with the highest position value of the counter are connected to comparison inputs of a digital number comparator and a decision output for the decision “counter value less than storage value” of the comparator is connected to a carry input of an adder, the first summand bit inputs of which are at the bit outputs of higher importance of the memory and whose second additive bit inputs are at zero potential and that the sum bit outputs of the adder are connected to bit inputs of a down counter, whose set signal input is connected to the carry output of the bits with the highest significance preceding bits of the counter is connected and its count input is connected to the same count pulse generator via an AND gate, the count pulses of which also act on the counter, a second input ang of the AND gate is connected via an inverter to the carry output of the down counter, at which the pulse-width modulated output signal of the digital-to-analog converter is also obtained.

Another digital-to-analog converter, which is also suitable for practicing the method according to the invention and which has a comparator, to whose comparison bit inputs bit outputs of a memory for a digital value to be converted on the one hand and bit outputs of a counter acted upon by the pulse train of a count pulse generator are connected on the other hand, whereby the groups of bit outputs of the counter are cyclically shifted with bit outputs of the memory which do not correspond in terms of position, and correspond to one another via the comparator and at the output of which a pulse-width-modulated signal can be taken off, is expediently set up in such a way that the output of the count pulse generator to the count input of the least significant bits following bits of the counter and the counting input of the least significant bits are connected to the carry output of the bits following the least significant bits and that a at a smaller count than that The respective memory content of the output of the least significant bits of the comparator which carries the signal is connected to an input of the following bits of the comparator originally provided for a signal which identifies a counter reading of the least significant bits of the comparator and the comparator has an output signal for a signal compared to the respective memory content delivers smaller or the same counter reading.

Storage and counters can be organized in binary form or in a mixed system. With a decadal system, powers of 10 can be achieved as factors for increasing the frequency of the output signal. The choice of factors is advantageously based on the frequency response of the available low pass.

The invention is explained below with reference to a drawing with four figures.

FIG. 1 shows a block diagram of an embodiment of a digital-to-analog converter for practicing the method according to the invention.

FIG. 2 also shows a block diagram of a second exemplary embodiment of a digital-to-analog converter for carrying out the method according to the invention.

FIG. 3 shows in table form the dependency of the output signal of the comparator of the digital-to-analog converter according to FIG. 2 on the compared input variables, namely the counter reading and the respective memory content.

FIG. 4 shows the output signal of the comparator of the digital-to-analog converter according to FIG. 2 in pulse form with a specific memory content.

In Figure 1, three decades of a counter Z can be seen, which are opposed by three decades of a memory Sp. The count input of the decade least significant value of the counter Z is connected to the output of a count pulse generator TG. Carry outputs of the previous decade are connected to count inputs of the following decades. Bit outputs of the decade of highest value of the counter Z are connected to comparison inputs A of a comparator HK. Corresponding bit inputs B of the comparator HK are connected to bit outputs of the decade of least importance of the memory Sp. Bit outputs of the decades following the decade of the least significant value of the memory Sp are connected to inputs C of adders Addi and Add2, which are also arranged in decades. Summation inputs D of the adders are at zero potential. Sum bit outputs I of adders Addi and Add2 are connected to bit inputs of two corresponding decades of a down counter RZ. A carry input of the adder Addi is connected to a decision output of the comparator HK which emits a signal when the numerical value accumulated in the decade of the highest value Z is less than the numerical value pending in the decade of the memory Sp. A carry output of an adder Addi is connected to a carry input of the adder Add2. A count input of the down counter RZ is connected via an AND gate G to the output of the count pulse generator TG. A second input of the AND gate G is connected via an inverter I to the carry output of the decade of highest priority of the down counter RZ. There is also a low pass T at this output, from which the analog value can be taken. The carry output of the decade lying between the decade lowest and the decade highest place value of the counter Z is connected to set inputs of the two decades of the down counter RZ.

The operation of this digital-to-analog converter is described below. The decades of counter Z, which is continuously counting, are shifted by one decade compared to the decades of memory Sp in the direction of increasing value on the memory side. The decade is the highest priority of the counter Z via the comparator HK of the decade of the lowest priority of the memory Sp

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across from. If the counter reading of the decade of highest priority of the counter is less than the content of the decade of lowest priority of memory Sp, comparator HK outputs a carry signal to adder Addi. The adder adds an increment to the value present in its summand bit inputs C s. The down counter is always set to this corrected total value when the counter Z emits a carry pulse of the decade lying between the decade lowest and the decade highest. The down counter RZ "> counts down from this value at the same frequency with which the counter Z counts up or down and stops,

when its content has gone to zero. It outputs an output signal until it is loaded again with a total value from the adders Addi and Add2. Due to the cyclical shift of the decades of the counter compared to those of the memory, the decades of the counter assigned to the higher decades of the memory run faster (for example by a factor of 10); only the decade of counters assigned to the decade of low significance of the memory runs 20 slower. It is therefore understandable that the above-mentioned output signal, a pulse-width-modulated square-wave signal, has a higher frequency than the prior art and therefore a less complex low-pass filter is sufficient for its integration. 25th

In FIG. 2, three decades of a counter Z are connected on the output side to corresponding comparison inputs A of three decades of a comparator K. Other comparison inputs B of the comparator K are connected to the bit outputs of three decades of a memory Sp. A low-pass filter T is connected to an output of the decade of highest value of the comparator K for the criterion A ^ B. The output of a count pulse generator TG is at the count input of the second decade of counter Z. The count input of the first decade of counter Z is at a carry output of the highest decade of counter Z. An output of the first decade of comparator K with criterion A < B is connected to the carry input of the second decade of the comparator K with the criterion A = B. Carry outputs of the second decade of comparator K with the three criteria A <B, A = B and A> B are connected to corresponding carry inputs of the highest decade of comparator K.

The table according to FIG. 3 shows the output signal of the comparator K as a discrete logical value depending on the decision criterion of the comparator decade of the lowest value on the one hand and the decision criterion of the higher-order decade of the comparator on the other hand. In the left column of the table are the decision criteria of the decade of least importance, in the middle column the criteria of the decade of higher importance and in the right column the output signal as log. "1" and log. "0" recorded. The logical values in the right-hand column of the table in FIG. 3 compose a pulse-width-modulated square-wave signal at the output of the comparator. For the reasons that were already mentioned in the circuit according to FIG. 1, it also applies to this signal that it has a higher frequency than output signals which have hitherto been achieved with digital-to-analog converters of the same type.

FIG. 4 shows the time course of the output signal of the comparator K for ten runs of the decade of least importance of the counter Z from 0 to 9. A memory content of the decade of least significance of 3 is assumed. It can be seen that within ten runs, the 3 contained in the decade of least significance in the counter is represented in the output voltage as three additional bits of 10 in the first three runs. It can also be seen that for A = B, the output signal of the comparator K becomes zero in the decade of least importance, since the carry input of the decade following the decade of least importance is no longer activated. The example shown in FIG. 4 relates to a decadal comparator K.

2 sheets of drawings

Claims (3)

646 823 PATENT CLAIMS 1. A method for converting a digital value into an analog value, in which the digital value contained in a number memory (Sp) is continuously compared with the content of a counter (Z) loaded by a counting pulse sequence and which range from an initial state of the counter (Z) to If the two numerical values expire, the pulse duty factor of a pulse signal is determined and in which, in order to increase the frequency of the pulse signal, at least one group of bit outputs of the counter (Z) are compared with bit outputs of the memory (Sp) which are not equivalent in terms of position, characterized in that all Bit outputs of the counter (Z) are cyclically shifted in relation to the bit outputs of the memory (Sp) to be compared in the direction of the position value increasing on the memory side, with bit outputs of the counter (Z) at the end of the highest value bit outputs of the memory ( Sp) at the end of the lowest place in the pre given number, and that an increment is added to the bits following the bits with the lowest position value of the memory (Sp), as long as the numerical value at the bit outputs with the lowest position value of the memory (Sp) contains the current content of the bits with the highest position value of the bits compared with it Counter (Z) exceeds. 2. A digital-to-analog converter for carrying out the method according to claim 1, characterized in that the bit outputs of the lowest place value of the memory (Sp) and the bit outputs of the highest place value of the counter (Z) are connected to comparison inputs of a digital number comparator (HK) and a Decision output for the decision "counter value less than storage value" of the comparator (HK) is connected to a carry input of an adder (Add 1), the first summand bit inputs (C) of which the bit outputs have higher significance in the memory (Sp) and the second summand bit inputs (D) are at zero potential, and that the sum bit outputs (I) of the adder (Add 1) are connected to bit inputs of a down counter (RZ), the set signal input of which is connected to the carry output of the bits of the counter (Z) preceding the most significant bits and the count input of which an AND gate (G) is connected to the same count generator (TG) that Sen count pulses also act on the counter (Z), a second input of the AND gate being connected via an inverter (I) to the carry output of the down counter (RZ), at which the pulse-width-modulated output signal of the digital-to-analog converter is also obtained. 3. Digital-to-analog converter for carrying out the method according to claim 1, with a comparator (K), at the comparison bit inputs of which bit outputs of a memory (Sp) for a digital value to be converted on the one hand and bit outputs of a counter acted upon by the pulse train of a count pulse generator (TG) ( Z) are connected on the other hand, the groups of bit outputs of the counter (Z) being cyclically shifted and corresponding to the bit outputs of the memory (Sp) which do not correspond in terms of position, correspond to one another via the comparator (K), and a pulse-width-modulated signal can be taken from the output thereof, characterized in that that the output of the counting pulse generator (TG) is connected to the counting input of the bits of the counter (Z) following the least significant bits and the counting input of the least significant bits to the carry output of the bits following the least significant bits, and that a smaller one Meter reading as the respective memory content signal-carrying output (A <B) of the least significant bits of the comparator (K) with an input (A = B) of the following bits of the signal originally intended for a counter reading of the least significant bits of the comparator (K) that is identical to the respective memory content Comparator (K) is connected and that the comparator (K) delivers an output signal at a smaller or the same counter reading compared to the respective memory content.