JPS6239821A - Manufacture of double-layer interconnection substrate - Google Patents

Manufacture of double-layer interconnection substrate

Info

Publication number
JPS6239821A
JPS6239821A JP17997885A JP17997885A JPS6239821A JP S6239821 A JPS6239821 A JP S6239821A JP 17997885 A JP17997885 A JP 17997885A JP 17997885 A JP17997885 A JP 17997885A JP S6239821 A JPS6239821 A JP S6239821A
Authority
JP
Japan
Prior art keywords
pixel electrode
upper pixel
electrode
lower transparent
ito
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17997885A
Other languages
Japanese (ja)
Other versions
JP2773111B2 (en
Inventor
Toshiro Nagase
俊郎 長瀬
Hisao Hoshi
久夫 星
Takeo Sugiura
杉浦 猛雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP60179978A priority Critical patent/JP2773111B2/en
Publication of JPS6239821A publication Critical patent/JPS6239821A/en
Application granted granted Critical
Publication of JP2773111B2 publication Critical patent/JP2773111B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing Of Electric Cables (AREA)

Abstract

PURPOSE:To simplify the manufacturing process, and to improve the yield of a product by utilizing a variation of a chemical property by a heat treatment of an ITO film which is formed by a low temperature spattering method, and forming an upper picture element electrode by means of etching. CONSTITUTION:An insulating layer 3 is formed on a glass base material 1 on which a lower transparent electrode 2 consisting of ITO is formed, and a through-hole 4 for obtaining an electric conduction between the upper and the lower electrodes is formed on the layer 3. Subsequently, an upper picture element electrode use ITO film 6 is formed on the whole surface by a low temperature spattering method, on the layer 3, and a photoresist pattern 7 is formed on the ITO film in order to form the upper picture element electrode pattern, and thereafter, chemical etching of the upper picture element electrode use ITO film is executed without exerting an influence on the electrode 2 by using an inorganic acid solution, and thereafter, the pattern 7 is removed and a heat treatment is executed. In such a way, a protecting process of the electrode 2 is not required, the process is simplified, the reliability is improved, and the yield can be improved.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、液晶ディスプレイ用二層配線基板の製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method of manufacturing a two-layer wiring board for a liquid crystal display.

(従来の技術とその問題点) 近年、液晶ディスプレイの実用化が一般化し、さらにそ
の応用分野が拡大するにつれ、ディスプレイの表示画素
数の増加が図られている。
(Prior Art and its Problems) In recent years, as the practical use of liquid crystal displays has become common and the fields of their application have expanded, attempts have been made to increase the number of display pixels of the display.

この表示画素数の増加に伴う、画面に対する画素面積占
有率(以下単に開孔率という)の減少を改善するたぬ二
層配線を用いた液晶ディスプレイ基板が考えられている
。即ち、従来の単層基板に於いて、各画素への配線は、
画素間のスペースに設置されている為、画素数が増加す
ると、この配線用スペースの占める面積は増大し、開孔
率の減少をもたらす。
A liquid crystal display substrate using tanu double-layer wiring is being considered to improve the decrease in pixel area occupancy (hereinafter simply referred to as aperture ratio) with respect to the screen due to the increase in the number of display pixels. In other words, in a conventional single-layer board, the wiring to each pixel is
Since it is installed in the space between pixels, as the number of pixels increases, the area occupied by this wiring space increases, resulting in a decrease in the aperture ratio.

そこで、この配線を各画素の下に絶縁層を介して設置し
、各画素と配線は、絶縁層に形成したスルーホールによ
り導通を得る様な二層配線構造により開孔率の向上が期
待できる。
Therefore, this wiring is installed under each pixel via an insulating layer, and each pixel and the wiring are connected to each other through a through hole formed in the insulating layer.This two-layer wiring structure can be expected to improve the aperture ratio. .

第1図は、液晶ディスプレイ用二層配線基板の概略図で
ある。
FIG. 1 is a schematic diagram of a two-layer wiring board for a liquid crystal display.

下部透明電極(2)を有するガラス基材(i)上に、絶
縁物からなる。絶縁層(3)を形成し、その上に透明導
電膜圧よる上部画素電極(5)を形成する。上部画素電
極(5)と下部透明電極(2)は、絶縁層(3)に形成
されたスルーボール(4)を介して導通を得る様な構造
を有する。この様な構造を有する液晶ディスプレイ用二
層配線基板を製造、する際に工程上大きな問題となるの
は、上部画素電極(5)の形成工程である。
It consists of an insulator on a glass substrate (i) having a lower transparent electrode (2). An insulating layer (3) is formed, and an upper pixel electrode (5) made of a transparent conductive film is formed thereon. The upper pixel electrode (5) and the lower transparent electrode (2) have a structure in which conduction is obtained through a through ball (4) formed in the insulating layer (3). When manufacturing a two-layer wiring board for a liquid crystal display having such a structure, a major problem arises in the process of forming the upper pixel electrode (5).

即ち、上部画素電極(5)は絶縁層(3)上全面に透明
導電膜を成膜後フォトエツチング法により所定のパター
ンに加工され番が、この時下部透明電極(2)は後から
成膜した上部画素電極用透明導電膜に覆われ電極間の短
絡が生ずる。また、上部画素電極(5)と下部透明電極
(2)は同じ材料であるので、上部画素電極(5)を化
学エツチングする際に下部透明電極(2)もエツチング
を受け、パターンの消失、抵抗値の増加等の欠陥が生ず
る。従来法では、この問題を除(ため、下部透明電極(
2)露出部に保護マスクを形成した後、全面に透明導電
膜を成膜し上部画素電極(5)を化学エツチングにより
パターン化を行ない下部透明電極保護マスクをリフトオ
フ法により除去するプロセス、或いは、下部透明電極露
出部保護と上部画素電極形成の2種を兼ねたリフトオフ
パターンを用い、全面に上部画素用透明導電膜を成膜後
リフトオフ法により上部画素電極(5)を形感するプロ
セスが行なわれていた。しかし、両プロセスに於て、工
程の煩雑性、リフトオフ工程の低信頼性による製品歩留
り率の不良が生じ、製品コスト上昇が避けられないとい
う欠点があった。
That is, the upper pixel electrode (5) is formed by forming a transparent conductive film on the entire surface of the insulating layer (3) and then processing it into a predetermined pattern by photo-etching.At this time, the lower transparent electrode (2) is formed later. The transparent conductive film for the upper pixel electrode causes a short circuit between the electrodes. Furthermore, since the upper pixel electrode (5) and the lower transparent electrode (2) are made of the same material, when the upper pixel electrode (5) is chemically etched, the lower transparent electrode (2) is also etched, resulting in loss of pattern and resistance. Defects such as an increase in value occur. In the conventional method, this problem is eliminated (in order to avoid this problem, the lower transparent electrode (
2) A process in which a protective mask is formed on the exposed portion, a transparent conductive film is formed on the entire surface, the upper pixel electrode (5) is patterned by chemical etching, and the lower transparent electrode protective mask is removed by a lift-off method, or After forming a transparent conductive film for the upper pixel over the entire surface using a lift-off pattern that serves both of protecting the exposed portion of the lower transparent electrode and forming the upper pixel electrode, a process is performed to form the upper pixel electrode (5) using the lift-off method. It was However, both processes have drawbacks such as poor product yield due to the complexity of the process and low reliability of the lift-off process, and an unavoidable increase in product costs.

(発明の目的) 本発明は、従来法に存する欠点に鑑み、液晶ディスプレ
イ用二層配線基板製造工程の簡素化を行ない製品の歩留
り向上を得る方法に関するものである。
(Object of the Invention) The present invention relates to a method of simplifying the manufacturing process of a two-layer wiring board for a liquid crystal display and improving the yield of the product in view of the drawbacks existing in the conventional method.

C問題点を解決する具体的手段) 即ち、基板温度を150℃以下の低温で成膜する低温ス
パッタリング法により成膜されたITO1膜の熱処理に
よる化学的性質の変化を利用し、゛下部透明電極の保護
マスクを形成する事なく上部画素電極をエツチングによ
り形成する方法に関するものである。さらに詳しく述べ
れば、低温スパッタリング法によ・り成膜されたIT、
O膜は、化学的安定性(特に耐塩化水素性)に劣り、通
常成膜後に250〜350℃の温度に於ける大気中加熱
処理により所定の化学的安定性を得ている。本発明は、
この点に着目したものであり、加熱処理済みの化学的に
安定なる下部透明電極上に低温スノくツタリング法によ
りITO膜を成膜しこのITO膜の化学的不安定性即ち
、エツチング容易性を利用し、下部透明電極を侵す事な
く上部画素電極用ITO膜を化学エツチング可能なる希
塩酸等の酸性エツチング液を用い、下部透明電極の保護
マスクを形成する事なく上部画素電極を化学エツチング
により形成する事、及び上部画素電極の化学的安定性を
向上するため250℃以上の温度で加熱処理を行なう事
により液晶ディスプレイ用二層配線基板を容易に得る方
法に関するものである。
(Specific means for solving problem C) That is, by utilizing the change in chemical properties caused by heat treatment of the ITO1 film formed by the low-temperature sputtering method in which the film is formed at a substrate temperature of 150°C or lower, the lower transparent electrode The present invention relates to a method of forming an upper pixel electrode by etching without forming a protective mask. More specifically, IT formed into a film by low-temperature sputtering method,
The O film has poor chemical stability (particularly resistance to hydrogen chloride), and usually obtains a certain level of chemical stability by heat treatment in the air at a temperature of 250 to 350° C. after film formation. The present invention
Focusing on this point, an ITO film is formed by a low-temperature snow splattering method on a chemically stable heat-treated lower transparent electrode, and the chemical instability of this ITO film, that is, its ease of etching, is utilized. However, the upper pixel electrode can be formed by chemical etching without forming a protective mask for the lower transparent electrode, using an acidic etching solution such as dilute hydrochloric acid that can chemically etch the ITO film for the upper pixel electrode without corroding the lower transparent electrode. The present invention also relates to a method for easily obtaining a two-layer wiring board for a liquid crystal display by performing heat treatment at a temperature of 250° C. or higher in order to improve the chemical stability of the upper pixel electrode.

(発明の詳細な 説明によるプロセスを第2図から第6図を用いて詳細に
説明する。
(The process according to the detailed description of the invention will be explained in detail using FIGS. 2 to 6.

第2図はITOより成る下部透明電極(2)が形成され
たガラス基材(i)である。このITOの下部透明電極
(2)の成膜方法は、いずれの方式によっても良いが成
膜時或いは成膜後200℃以上の温度で加熱処理を受け
たものでなければならない。第3・図は前記基材に絶縁
性を有する有機高分子又は無機化合物よりなる絶縁層(
3)を形成したものである。
FIG. 2 shows a glass substrate (i) on which a lower transparent electrode (2) made of ITO is formed. The ITO lower transparent electrode (2) may be formed by any method, but it must be heat-treated at a temperature of 200° C. or higher during or after film formation. Figure 3 shows an insulating layer (
3).

絶縁層(3)には、上下電極間の導通を得るためのスル
ーホ一ル(4)を形成する。スルーホール(4)は、絶
縁層(3)にフォトエツチング法又はリフトオフ法を用
いて形成するのが一般的であるが、感光性高分子を絶縁
層(3)に直接使用してスルーホール(4)をフォトリ
ングラフイーにより形成する事も可能である。また、液
晶ディスプレイ用基板として、絶縁層(3)は光透過率
の高い材料が望ましい。
A through hole (4) is formed in the insulating layer (3) to provide electrical continuity between the upper and lower electrodes. The through hole (4) is generally formed in the insulating layer (3) using a photoetching method or a lift-off method, but the through hole (4) is formed by directly using a photosensitive polymer in the insulating layer (3). 4) can also be formed by photophosphorography. Further, as a substrate for a liquid crystal display, the insulating layer (3) is preferably made of a material with high light transmittance.

次に第4図に示す様に、絶縁層(3)の上に低温スパッ
タリング法により全面に上部画素電極用ITO膜(6)
を成膜する。低温スパッタ法とは、成膜時の基材温度を
150℃以下に保持してスパッタリング成膜な行なう方
法を示し、この方法で得られた上部画素電極用ITO膜
(6)はエツチング性良好な、即ち、下部透明電極(2
)に比較して化学エツチングされ易い特性を有する。ガ
ラス基材(i)の温度は、低い程望ましく150℃以上
の場合、エッチ、ング選択性は損なわれるため150°
C以下に設定する。
Next, as shown in FIG. 4, an ITO film (6) for the upper pixel electrode is formed on the entire surface of the insulating layer (3) by low-temperature sputtering.
Deposit a film. The low-temperature sputtering method refers to a method in which sputtering film formation is performed while maintaining the substrate temperature at 150°C or less during film formation, and the ITO film (6) for the upper pixel electrode obtained by this method has good etching properties. , that is, the lower transparent electrode (2
) has the property of being easily chemically etched. The temperature of the glass substrate (i) is desirably as low as possible; if it is higher than 150°C, etching selectivity will be impaired;
Set to C or lower.

スパッタリング装置は、基材温度上昇を避けるためマグ
ネトロン方式スパッタリング装置が適しているが、他の
装置に於ても上記条件を満足すればこの限りではない。
As the sputtering apparatus, a magnetron type sputtering apparatus is suitable in order to avoid an increase in the temperature of the base material, but this is not limited to other apparatuses as long as they satisfy the above conditions.

またITO膜の原材料つまりターゲットに関して述べれ
ば、インジウム−スズ合金ターゲットと酸素雰囲気によ
る反応性スパッタリング法又はITOターゲットによる
通常のスパッタリング法の両者とも適用可能である。
Regarding the raw material for the ITO film, that is, the target, both a reactive sputtering method using an indium-tin alloy target and an oxygen atmosphere or a normal sputtering method using an ITO target are applicable.

次に第5図に示す様に上部画素電極パターンを形成する
ため、ITO膜上にフォトレジストパターン(力を形成
する。その後塩酸、硫酸、硝酸等の無機酸溶液を用いて
下部透明電極(2)に何ら彩管を与えずに上部画素電極
用ITO膜の化学エツチングを行なう。この時、使用す
る無機酸としては、塩酸が最も望ましく、2〜10体積
%の希塩酸が最良であった。
Next, in order to form the upper pixel electrode pattern as shown in FIG. ) The ITO film for the upper pixel electrode was chemically etched without providing any color tube.At this time, as the inorganic acid used, hydrochloric acid was the most desirable, and dilute hydrochloric acid of 2 to 10% by volume was the best.

第6図はフォトレジスト(7)パターンを除去後の二層
配線基板であり、パターン化された上部画素用電極(5
)の化学的安定性向上は、この基板を250℃以上の温
度で加熱処理する事により、従来の■TO膜と何ら遜色
のない性能が得られる。
Figure 6 shows the two-layer wiring board after removing the photoresist (7) pattern, and shows the patterned upper pixel electrode (5).
) By heat-treating this substrate at a temperature of 250° C. or higher, it is possible to obtain performance comparable to that of the conventional ①TO film.

(発明の効果) 以上の様に、従来液晶ディスプレイ用二層配線基板を製
造する際に、下部透明電極の保護工程が不可欠であり、
そのため製造工程の煩雑化及びそれに伴う信頼性、歩留
りの低下等の問題が有り、コスト上昇の大きな原因とな
っていたが、本発明によれば、下部透明電極の保護工程
は一切不要となり工程の簡略化、信頼性の向上、歩留り
の向上が可能となり大巾なコストダウンが可能となるも
のである。
(Effects of the Invention) As described above, when manufacturing a conventional two-layer wiring board for liquid crystal displays, a protection process for the lower transparent electrode is essential.
This has caused problems such as complicating the manufacturing process and reducing reliability and yield, which has been a major cause of cost increases.However, according to the present invention, there is no need to protect the lower transparent electrode at all, making the process easier. This enables simplification, improved reliability, and improved yield, making it possible to significantly reduce costs.

以下に実施例を示す。Examples are shown below.

〔実施例1〕 シリカコート(厚み1500k)されたソーダガラス基
材にITO膜をITOターゲットを使用してマグネトロ
ン方式の高周波スパッタリング装置で成膜を行なった。
[Example 1] An ITO film was formed on a silica-coated (thickness: 1500K) soda glass substrate using an ITO target using a magnetron-type high-frequency sputtering device.

この時の成膜雰囲気は5刈0−3Tonrのアルゴンガ
スである。
The film forming atmosphere at this time was argon gas at 0-3 Tonr.

また、膜厚は400^であり、基材加熱は行なわす、成
膜後350℃の温度で大気中30分間焼成を行なった。
The film thickness was 400^, and the base material was heated. After film formation, baking was performed in the air at a temperature of 350° C. for 30 minutes.

次に下部透明電極を形成するためポジレジスト(東京応
化製0FPR2)を用い、化学エツチング法によりパタ
ーンを形成した。この時のエツチング液組成は濃塩酸7
5体積%、塩化第2鉄溶液25体積%であり、液温は5
0℃であった。この基材上に透明性の良い感光性ポリイ
ミドをコートし、露光・現像を行ないスルーホールを形
成して絶縁層とl−た′。再び、ITOターゲットを使
用してマグネトロン方式高周波スパッタリング装置を使
用し、基材を常温に保ったまま、基材全面にITO膜を
400人の膜厚成膜した。(尚、前回と成膜条件は同じ
である)続いてポジレジスト(東京応化製OF P R
2)を使用して、露光・現像、焼付は後、5体積%濃度
の希塩酸で化学エツチングを行ない画素用電極を形成し
た。その後レジストを剥膜し、上部画素電極の耐薬品性
を自戒l〜だ。
Next, in order to form a lower transparent electrode, a pattern was formed by chemical etching using a positive resist (0FPR2 manufactured by Tokyo Ohka Co., Ltd.). The composition of the etching solution at this time was concentrated hydrochloric acid 7.
5% by volume, 25% by volume of ferric chloride solution, and the liquid temperature was 5% by volume.
It was 0°C. This base material was coated with highly transparent photosensitive polyimide, exposed and developed to form through holes, and formed into an insulating layer. Again, an ITO target was used and a magnetron type high frequency sputtering device was used to form an ITO film to a thickness of 400 mm over the entire surface of the substrate while keeping the substrate at room temperature. (The film forming conditions are the same as the previous time.) Next, positive resist (TOKYO OHKA OF PR) was applied.
After exposure, development, and baking using 2), chemical etching was performed with dilute hydrochloric acid at a concentration of 5% by volume to form a pixel electrode. After that, I peeled off the resist and tested the chemical resistance of the upper pixel electrode.

〔実施例2〕 真空蒸着法によりITO膜(膜厚1000″A、)が形
成されたソーダガラス基材に下部透明電極を形成するた
ぬ、ポジレジスト(シブレイAZ−1350)を用い化
学エツチング法によりパターン化を行なった。次に同じ
ポジレジストを使用して、スルーホール形成用リフトオ
フパターンを形成し、SiO2をマグネトロン方式高周
波スパッタリング装置により6000にの膜厚で成膜し
、絶縁層とした。スルーホールをリフトオフにより形成
した後、■n−Sn合金(8n 9重量%)をターゲッ
トに使用し基材温度を40℃に保ったまま、マグネトロ
ン方式直流スパッタリング装置により反応性スパッタリ
ングを行ない、基材全面にITO膜を600にの膜厚で
形成した。この時のスパッタリング雰囲気は、酸素分圧
が5.OX 10 ’Torr、アルゴン分圧が4.O
X I O”Torrであった。次にポジレジスト(シ
ブレイAZ−1350)  を使用して、レジストパタ
ーンを形成した後、3体積%濃度の希塩酸で化学エツチ
ングを行ない上部画素電極を形成した。
[Example 2] A lower transparent electrode was formed on a soda glass substrate on which an ITO film (thickness: 1000″A) was formed by vacuum evaporation, and chemical etching was performed using a positive resist (Sibley AZ-1350). Next, using the same positive resist, a lift-off pattern for forming through holes was formed, and a SiO2 film was formed to a thickness of 6000 mm using a magnetron type high frequency sputtering device to form an insulating layer. After forming through-holes by lift-off, reactive sputtering is performed using a magnetron DC sputtering device using an n-Sn alloy (8N 9% by weight) as a target and keeping the substrate temperature at 40°C. An ITO film was formed on the entire surface with a thickness of 600 mm.The sputtering atmosphere at this time had an oxygen partial pressure of 5.OX 10' Torr and an argon partial pressure of 4.0 Torr.
X I O'' Torr. Next, a resist pattern was formed using a positive resist (Sibley AZ-1350), and then chemical etching was performed with dilute hydrochloric acid at a concentration of 3% by volume to form an upper pixel electrode.

レジストを剥膜した後、350℃で30分間大気中で焼
成を行ない上部画素電極の耐薬品性の改善を行ない液晶
ディスプレイ用二層配線基板を完成した。
After peeling off the resist, baking was performed in the air at 350° C. for 30 minutes to improve the chemical resistance of the upper pixel electrode and complete a two-layer wiring board for a liquid crystal display.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明による二層配線基板の一例を示す斜視
図であり、第2図から第6図までは、□本発明の二層配
線基板の製造方法の一実施例を順に示す説明図である。 (i)・・・ガラス基材 (2)・・・下部透明電極 (3)・・・絶縁層 (4)・・・スルーホール (5)・・・上部画素電極 (6)・・・上部画素電極用ITO膜 (7)・・・フォトレジスト
FIG. 1 is a perspective view showing an example of a two-layer wiring board according to the present invention, and FIGS. 2 to 6 are explanations sequentially showing one embodiment of the method for manufacturing a two-layer wiring board according to the present invention. It is a diagram. (i)...Glass base material (2)...Lower transparent electrode (3)...Insulating layer (4)...Through hole (5)...Upper pixel electrode (6)...Top ITO film for pixel electrode (7)...photoresist

Claims (1)

【特許請求の範囲】 1)ITO(インジウム−スズ酸化物)を材料とする下
部透明電極を有するガラス基板上に有機物又は無機物よ
りなる絶縁層を介してITOを材料とする上部画素電極
を形成し、該上部画素電極と該下部透明電極間の導通は
絶縁層に形成したスルーホールにより得る構造を有する
液晶ディスプレイ用二層配線基板の製造方法において、 (i)スパッタリング成膜時の基材温度150℃以下で
行なう低温スパッタリング法により形成された上部画素
電極用ITO透明導電膜を下部透明電極に損傷を与えな
いエッチング液を用い選択的フォトエッチングして上部
画素電極とする工程、 (ii)エッチング終了後250℃以上の温度で基材を
加熱する工程、 を特徴とする液晶ディスプレイ用二層配線基板の製造方
法。
[Claims] 1) An upper pixel electrode made of ITO (indium-tin oxide) is formed on a glass substrate having a lower transparent electrode made of ITO (indium-tin oxide) via an insulating layer made of an organic or inorganic material. , in a method for manufacturing a two-layer wiring board for a liquid crystal display having a structure in which conduction between the upper pixel electrode and the lower transparent electrode is obtained by a through hole formed in an insulating layer, (i) a substrate temperature of 150 during sputtering film formation; A step of selectively photoetching the ITO transparent conductive film for the upper pixel electrode formed by a low-temperature sputtering method performed at temperatures below ℃ using an etching solution that does not damage the lower transparent electrode to form the upper pixel electrode, (ii) Completion of etching A method for manufacturing a two-layer wiring board for a liquid crystal display, comprising: heating a base material at a temperature of 250° C. or higher.
JP60179978A 1985-08-15 1985-08-15 Method for manufacturing double-layer wiring board Expired - Lifetime JP2773111B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60179978A JP2773111B2 (en) 1985-08-15 1985-08-15 Method for manufacturing double-layer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60179978A JP2773111B2 (en) 1985-08-15 1985-08-15 Method for manufacturing double-layer wiring board

Publications (2)

Publication Number Publication Date
JPS6239821A true JPS6239821A (en) 1987-02-20
JP2773111B2 JP2773111B2 (en) 1998-07-09

Family

ID=16075310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60179978A Expired - Lifetime JP2773111B2 (en) 1985-08-15 1985-08-15 Method for manufacturing double-layer wiring board

Country Status (1)

Country Link
JP (1) JP2773111B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0239128A (en) * 1988-07-29 1990-02-08 Hitachi Ltd Transparent insulating substrate with transparent conductive film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0239128A (en) * 1988-07-29 1990-02-08 Hitachi Ltd Transparent insulating substrate with transparent conductive film

Also Published As

Publication number Publication date
JP2773111B2 (en) 1998-07-09

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