JPH0239128A - Transparent insulating substrate with transparent conductive film - Google Patents
Transparent insulating substrate with transparent conductive filmInfo
- Publication number
- JPH0239128A JPH0239128A JP63188449A JP18844988A JPH0239128A JP H0239128 A JPH0239128 A JP H0239128A JP 63188449 A JP63188449 A JP 63188449A JP 18844988 A JP18844988 A JP 18844988A JP H0239128 A JPH0239128 A JP H0239128A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive film
- transparent conductive
- wiring
- transparent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 40
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 105
- 239000010409 thin film Substances 0.000 claims description 21
- 239000003990 capacitor Substances 0.000 claims description 18
- 239000011159 matrix material Substances 0.000 claims description 17
- 239000010410 layer Substances 0.000 claims description 9
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 7
- 230000014759 maintenance of location Effects 0.000 claims description 7
- 239000004973 liquid crystal related substance Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- 239000012780 transparent material Substances 0.000 claims 1
- 239000011521 glass Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Non-Insulated Conductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アクティブマトリクス基板をその一例として
含む、透明導電膜付透明絶縁基板の構造に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a transparent insulating substrate with a transparent conductive film, including an active matrix substrate as an example thereof.
透明導電膜は、透明絶縁基板は、液晶を用いたフラット
パネルデイスプレィ用の基板として、特にこの基板上に
薄膜スイッチング素子を形成したアクティブマトリクス
基板として、近年研究開発が盛んである。Transparent conductive films and transparent insulating substrates have been actively researched and developed in recent years as substrates for flat panel displays using liquid crystals, particularly as active matrix substrates on which thin film switching elements are formed.
従来アクティブマトリクス基板においては、特開昭５８
−１３０５６１号に記載のように、その基板上において
、次の第２図に示す様な構造の部分がある。Regarding conventional active matrix substrates, Japanese Patent Application Laid-Open No. 58
As described in No. 130561, there is a structure on the substrate as shown in FIG. 2 below.
第２図はアクティブマトリクス基板上の１部分である、
電荷保持用キャパシタの断面図を示す。１は透明絶縁性
基板、２は透明導電膜（酸化スズ。Figure 2 shows a portion on the active matrix substrate.
A cross-sectional view of a charge retention capacitor is shown. 1 is a transparent insulating substrate, 2 is a transparent conductive film (tin oxide).
酸化インジウムあるいはインジウムスズ酸化物）、３は
絶縁膜（Ｓ ｉ Ｏｘ等）、４は透明導電膜を表す、透
明導電膜２と、４と、それらの間の絶縁膜３とにより電
荷保持用キャパシタが形成されている。ここで、透明導
電膜４は薄膜トランジスタ等の薄膜スイッチング素子に
接続される画素電極であり、透明導電膜２は、一定電位
とする共通電極である。(indium oxide or indium tin oxide), 3 represents an insulating film (S i Ox, etc.), and 4 represents a transparent conductive film. The transparent conductive films 2 and 4 and the insulating film 3 between them form a charge retention capacitor. is formed. Here, the transparent conductive film 4 is a pixel electrode connected to a thin film switching element such as a thin film transistor, and the transparent conductive film 2 is a common electrode that is kept at a constant potential.
本構造において導明導電膜２は、絶縁膜３に覆われてい
る。そのため、透明導電膜２に電位を与えるために、絶
縁膜３にコンタクトホールを形成し、この穴と絶縁膜３
の上に配線を形成し、この配線を外側に引き出して、電
源と接続する必要がある。第２図の５はコンタクトホー
ル、６は金属配線、７はコンタク１一部を表す。In this structure, the electrically conductive film 2 is covered with an insulating film 3. Therefore, in order to apply a potential to the transparent conductive film 2, a contact hole is formed in the insulating film 3, and the contact hole is connected to the insulating film 3.
It is necessary to form wiring on top of it, pull it out to the outside, and connect it to the power supply. In FIG. 2, 5 represents a contact hole, 6 represents a metal wiring, and 7 represents a part of the contact 1.
従来、この電圧供給用の導電膜６はスパッタ法等により
アルミなどの金属を用いて形成していた。Conventionally, the conductive film 6 for supplying voltage has been formed using a metal such as aluminum by sputtering or the like.
上記従来技術は、第２図の、透明導電膜２と、アルミ等
の金属配線６とのコンタクト部７において、オーミック
コンタク１−がとれず、十分な動作が実現出来ないとい
う問題があった。これを以下詳細に説明する。The above-mentioned conventional technology has a problem in that ohmic contact 1- cannot be established at the contact portion 7 between the transparent conductive film 2 and the metal wiring 6 such as aluminum, as shown in FIG. 2, and sufficient operation cannot be achieved. This will be explained in detail below.
第３図の実線は、第２図の、透明導電膜２と、金属配線
６との間の電圧−電流特性を表す。電圧を印可しても、
１ｖ以下では、電流はほとんど流れず高抵抗であり、印
加電圧が１■を超えると。The solid line in FIG. 3 represents the voltage-current characteristic between the transparent conductive film 2 and the metal wiring 6 in FIG. 2. Even if voltage is applied,
When the voltage is below 1V, almost no current flows and the resistance is high, and when the applied voltage exceeds 1V.
電流が流れる、すなわちダイオ−特性を示す。このため
、金属配線６に基板外部から印加された電圧が、このコ
ンタクト部７を介して透明導電膜２に十分に印加されず
、透明導電膜に所望の電圧を与えることが出来ない。ま
た、一般に、アクティブマトリクス基板においては、交
流駆動を行うが、この場合、第３図の高抵抗部分は、電
荷保持用キャパシタ等の容量と接続されているため、い
わゆるＲＣ回路を形成して、動作の遅延を引きおこす。Current flows, that is, exhibits diode characteristics. For this reason, the voltage applied to the metal wiring 6 from outside the substrate is not sufficiently applied to the transparent conductive film 2 via this contact portion 7, making it impossible to apply a desired voltage to the transparent conductive film. Generally, active matrix substrates are driven by alternating current, but in this case, the high-resistance portion shown in FIG. 3 is connected to a capacitor such as a charge holding capacitor, so that a so-called RC circuit is formed. This causes a delay in operation.
電圧−電流特性が第３図の様なダイオード特性を持つ理
由は、次のとおりである。The reason why the voltage-current characteristics have diode characteristics as shown in FIG. 3 is as follows.
第２図の透明導電膜２は、酸化スズ、酸化インジウム、
またはインジウムスズ酸化物であるが、これらは、その
膜中に酸素を含んでいる。そのため、アルミ等の金属配
線６と透明導電膜２との間の、コンタクト部７において
は、このアルミ等の金属配線が酸化され、絶縁性の酸化
膜が形成される。そのため、高電界を印加しない限り、
このコンタクト部７は電流を通さない。The transparent conductive film 2 in FIG. 2 includes tin oxide, indium oxide,
Or indium tin oxide, which contains oxygen in its film. Therefore, in the contact portion 7 between the metal wiring 6 made of aluminum or the like and the transparent conductive film 2, the metal wiring made of aluminum or the like is oxidized to form an insulating oxide film. Therefore, unless a high electric field is applied,
This contact portion 7 does not conduct current.
また、第２図の製造プロセスにおいて、たとえば、スイ
ッチング素子として多結晶シリコンを用いた薄膜トラン
ジスタを用いたアクティダマ１−リクス基板においては
、一般にプロセスの温度が５００℃〜１０００℃程度と
高い。この様な高温にコンタクト部７がさらされると、
アルミ等の金属配線６の酸化が促進され、電圧−電流特
性は第３図の点線に示す様に、高温にさらされない場合
に比べて一層悪くなる。In addition, in the manufacturing process shown in FIG. 2, for example, in the case of an actidamerix substrate using a thin film transistor using polycrystalline silicon as a switching element, the process temperature is generally as high as about 500 DEG C. to 1000 DEG C. When the contact portion 7 is exposed to such high temperatures,
Oxidation of the metal wiring 6 made of aluminum or the like is promoted, and the voltage-current characteristics become worse than when not exposed to high temperatures, as shown by the dotted line in FIG.
本発明の目的は、絶縁膜に覆われた透明導電「と、これ
に電気を印加するための配線との安定かつ、すぐれたコ
ンタクト特性を示す構造を提供することにある。An object of the present invention is to provide a structure that exhibits stable and excellent contact characteristics between a transparent conductor covered with an insulating film and wiring for applying electricity thereto.
上記目的は、絶縁膜に覆われた透明導電膜に対してコン
タクトホールを介してコンタク１−をとる配線を、その
透明導電膜と同じ暎によって形成することにより、達成
される。The above object is achieved by forming a wiring that makes contact with a transparent conductive film covered with an insulating film through a contact hole using the same method as that of the transparent conductive film.
絶縁膜によって覆われた透明導電膜と、それに対してコ
ンタクトホールを介してコンタクトをとる配線が同じ膜
であるため、これら２つのコンタクト面には、コンタク
ト不良の原因となる絶縁膜が形成されることはない。よ
って、良好なオーミックコンタクトが得られる。Since the transparent conductive film covered by the insulating film and the wiring that makes contact with it through the contact hole are the same film, an insulating film is formed on these two contact surfaces, which can cause contact failure. Never. Therefore, good ohmic contact can be obtained.
また、多結晶シリコンを用いたＴＰＴにより構成された
アクティブマトリクス基板においても、プロセス温度が
高いことによりコンタク１〜特性の低下がおこらない。Further, even in an active matrix substrate made of TPT using polycrystalline silicon, the contact characteristics do not deteriorate due to the high process temperature.
以下、本発明の実施例を第１図、第４図、第５図、第６
図を用いて説明する。Embodiments of the present invention will be described below with reference to FIGS. 1, 4, 5, and 6.
This will be explained using figures.
第４図は、アクティブマトリクス基板の説明図であり、
等価回路を表す９８は薄膜トランジスタ、９は電荷保持
用キャパシタ、１０は、液晶層の容量、１１は、走査線
、１２は信号線、１３は、走査線と信号線のクロス部、
１４は、電荷保持用キャパシタの、共通電極に電位を与
えるための配線、１５は、配線１４に電気を印加するた
めの、外部電源とのコンタクト部分を表す。１６の点線
で囲まれた領域は表示部を表す。表示部１６はこの様に
薄膜トランジスタとキャパシタがマトリクス状に形成さ
れている。FIG. 4 is an explanatory diagram of an active matrix substrate,
98 representing an equivalent circuit is a thin film transistor, 9 is a capacitor for charge retention, 10 is a capacitor of a liquid crystal layer, 11 is a scanning line, 12 is a signal line, 13 is a cross section between the scanning line and the signal line,
Reference numeral 14 represents a wiring for applying a potential to the common electrode of the charge holding capacitor, and reference numeral 15 represents a contact portion with an external power source for applying electricity to the wiring 14. The area surrounded by 16 dotted lines represents the display section. In this way, the display section 16 has thin film transistors and capacitors formed in a matrix.
走査線１°１は走査回路にコンタクト部分１７によって
接続され、また、信号ＮｆＡ１２は、コンタクト部分１
８によって信号回路に接続される。これら走査回路と信
号回路は、アクティブマトリクス基板とは別にＬＳＩ等
で構成され、基板に接続する場合や、表示部１６と同一
基板上に形成される場合がある。また、電荷保持用キャ
パシタ９は、液晶層の容量１０のみでは１Ｍｌ荷の保持
が十分でない場合にこの容量１０と並列して設ける電荷
の保持特性を改善するものであり、表示部１Ｇの設計に
よって必要である場合とそうでない場合がある。Scanning line 1°1 is connected to the scanning circuit by contact portion 17, and signal NfA12 is connected to contact portion 1
8 to the signal circuit. These scanning circuits and signal circuits may be formed of an LSI or the like separately from the active matrix substrate, and may be connected to the substrate, or may be formed on the same substrate as the display section 16. The charge retention capacitor 9 is provided in parallel with the liquid crystal layer capacitor 10 to improve the charge retention characteristic when the capacitance 10 of the liquid crystal layer alone is not sufficient to retain 1Ml. Sometimes it's necessary and sometimes it's not.
第１図に、第４図のコンタクト部１７に対して本発明を
実施した例を示す。第１図（、）は、コンタクト部１８
、第１図（ｂ）は表示部の１画素の薄膜トランジスタの
断面図を示す。FIG. 1 shows an example in which the present invention is applied to the contact portion 17 of FIG. 4. In FIG. FIG. 1 (,) shows the contact portion 18.
, FIG. 1(b) shows a cross-sectional view of a thin film transistor of one pixel in the display section.
ガラス基板１９の上に多結晶シリコン、アモルファスシ
リコン等の半導体膜２０をＣＶＤ法等によって形成し、
その上に、ゲート絶縁膜２１を形成し、ゲート電極２２
を自己整合的に形成する。A semiconductor film 20 made of polycrystalline silicon, amorphous silicon, etc. is formed on a glass substrate 19 by a CVD method or the like.
A gate insulating film 21 is formed thereon, and a gate electrode 22 is formed.
is formed in a self-consistent manner.
イオン打込み法などによりソース領域２３．ドレイン領
域２４を形成し、この様にしてコプレナー型の薄膜トラ
ンジスタを形成する。次に、インジウムスズ酸化物等の
透明導電膜を全面に形成し、パターニングして第４図の
信号線１２に相当する信号線２５、及び画素電極２６を
形成する。ここで信号線２５は、ソース領域２３に、ま
た画素電極２６はドレイン領域２４に接続されている。The source region 23. is formed by ion implantation or the like. A drain region 24 is formed, and a coplanar thin film transistor is thus formed. Next, a transparent conductive film such as indium tin oxide is formed on the entire surface and patterned to form a signal line 25 corresponding to the signal line 12 in FIG. 4 and a pixel electrode 26. Here, the signal line 25 is connected to the source region 23 and the pixel electrode 26 is connected to the drain region 24.
この上に、Ｓ ｉ ０２などの絶縁膜をＣＶＤ法等によ
って形成し１層間絶縁膜２７とする。層間Ｍ縁股２７に
対し、コンタクトホール２８．．２９を開け、次にこの
上に透明導電膜２５と同じ膜を形成し、この膜をパター
ニングして配線３０．及び第４図の走査線１１に対応す
る走査線３１を形成する。On top of this, an insulating film such as S i 02 is formed by a CVD method or the like to form a single interlayer insulating film 27 . A contact hole 28. ．． 29 is opened, then a film similar to the transparent conductive film 25 is formed thereon, and this film is patterned to form the wiring 30. Then, a scanning line 31 corresponding to the scanning line 11 in FIG. 4 is formed.
配線２９は、信号線と信号回路との接続に用いるための
配線であり、また第４図の２層配線部１３は、第７図に
おいて層間絶縁膜２７によって信号線、走査線を絶縁分
離する構造となっている。The wiring 29 is a wiring used to connect a signal line and a signal circuit, and the two-layer wiring section 13 in FIG. 4 insulates and separates the signal line and the scanning line by an interlayer insulating film 27 in FIG. It has a structure.
第１図において１層間絶縁膜２７によって信号線２５が
覆われているため、これに信号電圧を印可するためにコ
ンタクトホール２８によって基板の表面に配線２８を設
け、信号回路と接続してこのコンタクトホール２８は、
第４図のコンタクト部１８に相当する。ここで、配線３
ｏは、信号線２５と同じ膜を用いているため、コンタク
トホール２８においてオーミックに信号線２５と接続さ
れる。従来、配線３０は、アルミなどの金属を用いてい
タカ、これに比べ１木刀式では十分にコンタクト抵抗の
小さい、良好なオーミックコンタクトが得られる。その
ため動作の遅延などを引き起こすことがない。In FIG. 1, since the signal line 25 is covered by the first interlayer insulating film 27, a wiring 28 is provided on the surface of the substrate through a contact hole 28 in order to apply a signal voltage thereto, and the wiring 28 is connected to the signal circuit. Hall 28 is
This corresponds to the contact portion 18 in FIG. 4. Here, wiring 3
Since the same film as the signal line 25 is used for the signal line 25, it is ohmically connected to the signal line 25 through the contact hole 28. Conventionally, the wiring 30 has been made of a metal such as aluminum, but compared to this, the single-bokuto type allows a good ohmic contact with sufficiently low contact resistance to be obtained. Therefore, there will be no delay in operation.
また、本構造では、走査線、信号線ともに、透明導電膜
を用いている。従来、これらはアルミなどの金属を用い
ていたが、この場合は、透過光が光によって乱反射さり
、表示特性を低下させるという問題が生じるが本構造で
は、これらが透明膜で形成されているため、その様な問
題はおこらない。Further, in this structure, a transparent conductive film is used for both the scanning line and the signal line. Conventionally, metals such as aluminum were used for these, but in this case, there was a problem in that the transmitted light was diffusely reflected by the light, degrading the display characteristics, but in this structure, these are made of a transparent film. , such problems will not occur.
また、本実施例において、薄膜トランジスタの形成法及
び構造は第１図（ｂ）に示した例に限るものではなく、
たとえば、逆スタが構造等の薄膜トランジスタにおいて
も、第１図（ａ）に示したコンタクト構造を持つ場合に
おいて、同様に適用可能なものである。In addition, in this example, the formation method and structure of the thin film transistor are not limited to the example shown in FIG. 1(b).
For example, the present invention can be similarly applied to a thin film transistor having an inverted star structure or the like having the contact structure shown in FIG. 1(a).
また、本実施例は、信号線が絶縁膜に覆われている場合
の実施例であるが、逆に、走査線が層間絶縁膜２７によ
って覆われている場合においても、本発明は走査線と走
査回路との第４図におけるコンタクト部１７を第１図（
ａ）と同様の構造とすることによって適用できる。Further, although this embodiment is an example in which the signal line is covered with an insulating film, conversely, even when the scanning line is covered with the interlayer insulating film 27, the present invention can be applied to the scanning line as well. The contact portion 17 in FIG. 4 with the scanning circuit is shown in FIG. 1 (
This can be applied by having a structure similar to a).
第５図に、第１図のクロス部１３に対して、本発明を実
施した例を示す。第５図（ａ）はクロス部１３．第５図
（ｂ）は１画素の薄膜トランジスタのそれぞれ断面を示
す。FIG. 5 shows an example in which the present invention is applied to the cross portion 13 of FIG. 1. FIG. 5(a) shows the cross section 13. FIG. 5(b) shows a cross section of each thin film transistor of one pixel.
薄膜トランジスタを第１図と同様に形成後、インジウム
スズ酸化物等の透明導電膜の配線３２を形成する。この
上に、５ｉＯｚなどの絶縁膜を用いて層間絶縁膜３３を
形成する。次にこの層間絶縁膜に対してコンタクトホー
ル３４，３５を開口し、次にこの上に透明導電膜３２と
同じ透明導電膜を形成後、パターニングを行って、信号
線３６゜走査線３７．及び画素部Ｖｉ４３８を形成する
。After forming a thin film transistor in the same manner as in FIG. 1, a wiring 32 of a transparent conductive film such as indium tin oxide is formed. On top of this, an interlayer insulating film 33 is formed using an insulating film of 5iOz or the like. Next, contact holes 34 and 35 are opened in this interlayer insulating film, and then a transparent conductive film similar to the transparent conductive film 32 is formed thereon, and then patterned to form signal lines 36° scanning lines 37 . and a pixel portion Vi438.
第５図（ｂ）においては、信号線３６と、走査線３７が
同一平面内にある。そのため、第４図における走査線と
信号線とのクロス部１３において、これらがショートし
ない様に第５図（ａ）に示した２層配線を行う必要があ
る。本図の配線３１は、信号線３７と同じ膜によって形
成されているため、コンタクトホール３４における、配
線３１と、信号線３７とのコンタクトはオーミックとな
り、動作の遅延を引きおこすことがない。In FIG. 5(b), the signal line 36 and the scanning line 37 are in the same plane. Therefore, it is necessary to perform two-layer wiring as shown in FIG. 5(a) at the cross section 13 between the scanning line and the signal line in FIG. 4 so that these lines do not short-circuit. Since the wiring 31 in this figure is formed of the same film as the signal line 37, the contact between the wiring 31 and the signal line 37 in the contact hole 34 is ohmic, and does not cause any delay in operation.
本実施例は、第４図のクロス部１３における実施例であ
るが、表示部１６と同一基板上に非線形素子として画素
部と同じ薄膜トランジスタによって走査回路、及び信号
回路を形成する場合において、その回路の配線クロス部
分にも用いることができる。This embodiment is an example of the cross section 13 in FIG. 4, but when a scanning circuit and a signal circuit are formed on the same substrate as the display section 16 using the same thin film transistor as the pixel section as a nonlinear element, the circuit It can also be used for wiring cross sections.
第６図は、第１図のコンタクト部１５に対して、本発明
を実施した例を示す。第６図（ａ）は、コンタクト部、
第６図（ｂ）は、１画素における薄膜トランジスタ、及
び電荷保持用キャパシタの断面図を示す。FIG. 6 shows an example in which the present invention is applied to the contact portion 15 of FIG. FIG. 6(a) shows the contact part,
FIG. 6(b) shows a cross-sectional view of a thin film transistor and a charge holding capacitor in one pixel.
ガラス基板１９の上に、第１図（ｂ）と同様にし薄膜ト
ランジスタを形成後、インジウムスズ酸化物等の透明導
電膜３９を形成する。この」二に、容量用絶縁膜４０を
形成後、コンタクトホール４１．４３を形成して、その
」二に、透明導電膜３９と同じ透明導電膜を形成後、パ
ターニングして配線４２、及び画素電極３８を形成する
。After forming a thin film transistor on the glass substrate 19 in the same manner as in FIG. 1(b), a transparent conductive film 39 of indium tin oxide or the like is formed. After forming the capacitor insulating film 40, contact holes 41 and 43 are formed on this second layer, and after forming the same transparent conductive film as the transparent conductive film 39 on the second layer, patterning is performed to form the wiring 42 and the pixel. Electrodes 38 are formed.
本図において、透明導電膜３９のうち、４４の部分と画
素電極３８によって、電荷保持用キャパシタが形成され
ている。４４は、このキャパシタの片方の電極であり、
一定電位とする共通電極となる。また、この透明導電膜
３９のうち、４５の部分は、第１図の共通電極の配線１
４に対応している。また配線４２は、共通電極４４に電
圧を供給するための配線であり、この基板の外部に設け
られた電源と接続される。In this figure, a portion 44 of the transparent conductive film 39 and the pixel electrode 38 form a charge holding capacitor. 44 is one electrode of this capacitor,
It becomes a common electrode that maintains a constant potential. In addition, a portion 45 of this transparent conductive film 39 is connected to the wiring 1 of the common electrode in FIG.
It corresponds to 4. Further, the wiring 42 is a wiring for supplying voltage to the common electrode 44, and is connected to a power source provided outside the substrate.
本実施例において配線４２と、透明導電膜３９は同じ膜
である。よってコンタクト部４１において、安定かつ良
好なオーミックコンタク１−が得られ、動作の遅延をお
こすことがない。In this embodiment, the wiring 42 and the transparent conductive film 39 are the same film. Therefore, a stable and good ohmic contact 1- can be obtained in the contact portion 41, and there will be no delay in operation.
本発明によれば、アクティブマトリクス基板において、
絶縁膜によって覆われたインジウムスズ酸化物等の透明
導電膜に対して、安定かつ優れたオーミックコンタクト
をとることが出来るので、動作の遅延が抑えられ、この
アクティブマトリクス基板を用いた液晶表示装置の表示
特性を良好にすることが出来る。According to the present invention, in the active matrix substrate,
Since it is possible to make stable and excellent ohmic contact with a transparent conductive film such as indium tin oxide covered with an insulating film, operational delays can be suppressed, making it possible for liquid crystal display devices using this active matrix substrate to Display characteristics can be improved.
第１図はコンタクト部の断面図、第２図は従来技術の断
面図、第３図は透明導電膜と金属配線との電圧電流特性
図、第４図はアクティブマトリクス基板の説明図、第５
図はクロス部を示す図、第６図はコンタクト部を示す図
である。
１９・・・ガラス基板、２５・・・信号線、２７・・・
層間絶縁膜、２８・・・コンタクトホール、３０・・・
配線。
３２・・・配線、３３・・・層間絶縁膜、３４・・・コ
ンタクトホール、３７・・・走査線、３９・・・透明導
電膜、４０・・・容量用絶縁膜、４１：・コンタクトホ
ール、第
図
（α）
第３
’：１’： ６図
（α）Fig. 1 is a cross-sectional view of the contact part, Fig. 2 is a cross-sectional view of the conventional technology, Fig. 3 is a voltage-current characteristic diagram of the transparent conductive film and metal wiring, Fig. 4 is an explanatory diagram of the active matrix substrate, and Fig. 5 is a cross-sectional view of the contact part.
The figure shows the cross part, and FIG. 6 shows the contact part. 19...Glass substrate, 25...Signal line, 27...
Interlayer insulating film, 28... contact hole, 30...
wiring. 32... Wiring, 33... Interlayer insulating film, 34... Contact hole, 37... Scanning line, 39... Transparent conductive film, 40... Capacitor insulating film, 41: Contact hole , Figure (α) 3rd ':1': Figure 6 (α)
Claims (1)
いはインジウムスズ酸化物の第１の透明導電膜を形成し
、その透明導電膜上にＳｉＯ＿２膜等の絶縁膜を形成し
、その絶縁膜に第１の透明導電膜に対するコンタクトホ
ールを形成し、絶縁膜上に第２の導電膜による配線を形
成して、この第２の導電膜によって、第１の透明導電膜
との電気的コンタクトをとる構造の透明導電膜と、絶縁
膜、導電膜を具備する透明導電膜付透明絶縁基板におい
て、第２の導電膜の配線を、第１の透明導電膜と同じ膜
を用いることを特徴とした透明導電膜付透明絶縁基板。 ２、透明絶縁基板として、その基板上に薄膜スイッチン
グ素子及び透明導電膜、駆動電極からなる画素回路をマ
トリクス状に形成し、薄膜スイッチング素子間を結ぶ信
号配線と走査配線の２層配線のうち、少なくともその２
層配線の間の層間絶縁膜の下に形成された片方の配線を
、透明導電膜によって形成した液晶表示装置におけるア
クティブマトリクス基板を用いた場合において、その層
間絶縁膜の下に形成された透明導電膜による配線に対す
る層間絶縁膜を介したコンタクトを、この配線に用いた
ものと同じ透明導電膜の配線によって行うことを特徴と
する特許請求の範囲第１項記載の透明導電膜付透明絶縁
基板。 ３、透明絶縁性基板として、その基板上に薄膜スイッチ
ング素子及び透明導電膜、駆動電極からなる画素回路を
マトリクス状に形成し、加えて、各画素に対して、一定
電位とする共通電極を透明導電膜によって形成し、その
上に容量形成用の絶縁膜を形成し、その上に薄膜スイッ
チング素子と接続された画素電極を透明導電膜で形成し
、これら２枚の透明導電膜によって容量用絶縁膜をはさ
んだ構造を持つ電荷保持用キャパシタを形成した電荷保
持用キャパシタ付アクテイブマトリクス基板を用いた場
合において、一定電位とする共通電極に、容量用絶縁膜
を介してコンタクトをとるに際して、コンタクトホール
の形成後、この共通電極を形成したものと同じ透明導電
膜の配線を用いたコンタクトをとることを特徴とする特
許請求の範囲第１項記載の透明導電膜付透明絶縁基板。 ４、薄膜スイッチング素子として、多結晶シリコンを用
いた薄膜トランジスタを用いたことを特徴とする特許請
求の範囲第２項または第３項記載のアクティブマトリク
ス基板。[Claims] 1. A first transparent conductive film of indium oxide, tin oxide, or indium tin oxide is formed on a transparent insulating substrate, and an insulating film such as a SiO_2 film is formed on the transparent conductive film. , forming a contact hole for the first transparent conductive film in the insulating film, forming a wiring using a second conductive film on the insulating film, and connecting the first transparent conductive film with the second conductive film. In a transparent insulating substrate with a transparent conductive film having a structure for making electrical contact, an insulating film, and a conductive film, the same film as the first transparent conductive film is used for the wiring of the second conductive film. A transparent insulating substrate with a transparent conductive film. 2. As a transparent insulating substrate, a pixel circuit consisting of a thin film switching element, a transparent conductive film, and a drive electrode is formed in a matrix on the substrate, and among the two layers of signal wiring and scanning wiring that connect the thin film switching elements, at least part 2
When using an active matrix substrate in a liquid crystal display device in which one of the wirings formed under the interlayer insulating film between the layer wirings is formed with a transparent conductive film, the transparent conductive film formed under the interlayer insulating film is used. 2. The transparent insulating substrate with a transparent conductive film according to claim 1, wherein contact with the film wiring via the interlayer insulating film is made by wiring of the same transparent conductive film used for this wiring. 3. As a transparent insulating substrate, a pixel circuit consisting of a thin film switching element, a transparent conductive film, and a drive electrode is formed in a matrix on the substrate, and in addition, a common electrode that has a constant potential for each pixel is made of a transparent material. A pixel electrode is formed using a conductive film, an insulating film for forming a capacitance is formed on the insulating film, a pixel electrode connected to a thin film switching element is formed on the pixel electrode using a transparent conductive film, and the insulating film for capacitance is formed by these two transparent conductive films. When using an active matrix substrate with a charge retention capacitor formed with a charge retention capacitor having a structure sandwiching a film, a contact hole is required to make contact with a common electrode at a constant potential through a capacitor insulating film. 2. The transparent insulating substrate with a transparent conductive film according to claim 1, wherein after the common electrode is formed, contact is made using the same transparent conductive film wiring as that on which the common electrode is formed. 4. The active matrix substrate according to claim 2 or 3, wherein a thin film transistor using polycrystalline silicon is used as the thin film switching element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18844988A JP3053093B2 (en) | 1988-07-29 | 1988-07-29 | Active matrix liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18844988A JP3053093B2 (en) | 1988-07-29 | 1988-07-29 | Active matrix liquid crystal display |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23210397A Division JP3233076B2 (en) | 1997-08-28 | 1997-08-28 | Active matrix liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0239128A true JPH0239128A (en) | 1990-02-08 |
| JP3053093B2 JP3053093B2 (en) | 2000-06-19 |
Family
ID=16223889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18844988A Expired - Lifetime JP3053093B2 (en) | 1988-07-29 | 1988-07-29 | Active matrix liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3053093B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06258670A (en) * | 1992-12-10 | 1994-09-16 | Gold Star Co Ltd | Liquid-crystal display device and its preparation |
| US6713783B1 (en) | 1991-03-15 | 2004-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Compensating electro-optical device including thin film transistors |
| JP2014016631A (en) * | 2013-09-05 | 2014-01-30 | Semiconductor Energy Lab Co Ltd | Semiconductor device, module, and electronic apparatus |
| JP2014067057A (en) * | 2000-02-22 | 2014-04-17 | Semiconductor Energy Lab Co Ltd | Display device |
| JP2014123137A (en) * | 2000-08-14 | 2014-07-03 | Semiconductor Energy Lab Co Ltd | Display device |
| JP2015014799A (en) * | 2014-08-25 | 2015-01-22 | 株式会社半導体エネルギー研究所 | Display device, module, and electronic apparatus |
| US9059216B2 (en) | 2000-12-11 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5940582A (en) * | 1982-08-30 | 1984-03-06 | Seiko Epson Corp | Semiconductor device |
| JPS6239821A (en) * | 1985-08-15 | 1987-02-20 | Toppan Printing Co Ltd | Manufacture of double-layer interconnection substrate |
-
1988
- 1988-07-29 JP JP18844988A patent/JP3053093B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5940582A (en) * | 1982-08-30 | 1984-03-06 | Seiko Epson Corp | Semiconductor device |
| JPS6239821A (en) * | 1985-08-15 | 1987-02-20 | Toppan Printing Co Ltd | Manufacture of double-layer interconnection substrate |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6713783B1 (en) | 1991-03-15 | 2004-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Compensating electro-optical device including thin film transistors |
| JPH06258670A (en) * | 1992-12-10 | 1994-09-16 | Gold Star Co Ltd | Liquid-crystal display device and its preparation |
| JP2014067057A (en) * | 2000-02-22 | 2014-04-17 | Semiconductor Energy Lab Co Ltd | Display device |
| US9318610B2 (en) | 2000-02-22 | 2016-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US9869907B2 (en) | 2000-02-22 | 2018-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| JP2019197232A (en) * | 2000-02-22 | 2019-11-14 | 株式会社半導体エネルギー研究所 | Liquid crystal display device |
| JP2014123137A (en) * | 2000-08-14 | 2014-07-03 | Semiconductor Energy Lab Co Ltd | Display device |
| US9059216B2 (en) | 2000-12-11 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| US9666601B2 (en) | 2000-12-11 | 2017-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| US10665610B2 (en) | 2000-12-11 | 2020-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| JP2014016631A (en) * | 2013-09-05 | 2014-01-30 | Semiconductor Energy Lab Co Ltd | Semiconductor device, module, and electronic apparatus |
| JP2015014799A (en) * | 2014-08-25 | 2015-01-22 | 株式会社半導体エネルギー研究所 | Display device, module, and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3053093B2 (en) | 2000-06-19 |
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