JPH05203985A - Thin-film transistor array and its production and production of liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain the thin-film transistor(TFT) array which is applied with a remedy for static electricity and has high reliability and yield by previously forming the junctures of gate bus wirings and source bus wirings of conductive layers which can be anodized, maintaining these wirings at the same same potential and anodizing the junctures at need to form the structure to allow the insulation and sepn. thereof. CONSTITUTION:The source bus wirings 7 and source electrodes 8 of the TFTs and drain electrodes 9 of the TFTs are selectively deposited and formed of aluminum. The apertures 15 of the junctures 10 of the source and bus wirings 7 to each other are simultaneously coated so that the gate bus wirings and the source bus wirings are kept at the same potential. Apertures 13 and 14 are also provided in the junctures 4 of the gate bus wirings and the junctures 10 of the source bus wirings 7. The aluminum exposed in the apertures 13 and 14 is thereafter anodized by utilizing the electrodes 17 and 18 connecting the gate buses and the source buses to the outside as electric power supplying terminals for anodic oxidation at need, by which the gate bus and source bus wirings 7 are insulated and separated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array applied to a display device, a line sensor and the like, a manufacturing method thereof, a liquid crystal display device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, expectations for flattening of image display devices have increased, and research and development in this field have been very actively carried out. Among them, flat panel displays using liquid crystals are the most promising as commercialization has been advanced.

One of the flat displays that realizes high image quality using liquid crystals is an active matrix type liquid crystal display device in which unit picture elements composed of active elements such as transistors and liquid crystal optical elements are arranged in a two-dimensional matrix. ..
(FIG. 4) shows an equivalent circuit thereof, 21 is a scanning signal line, 2
2 the video signal line, 23 is a thin film transistor (T hin F ilm
T ransistor: abbreviated in TFT or less), 24 is a liquid crystal cell. A gate signal is sequentially applied to the scanning signal line 21 so that the thin film transistor 23 is turned on, and a video signal corresponding to one scanning line is written from the video signal line 22 to the liquid crystal cell 24. Line sequential scanning is equivalent to CRT. Function is granted.

Now, FIG. 5 shows the structure of an active matrix array using thin film transistors as an active matrix array for liquid crystal display. 21 is a scanning line (gate bus), 22 is a video signal line (source bus), 2
Reference numeral 3 is a thin film transistor as an active element, 25 is a pixel electrode, 26 and 27 are electrodes connected to an external drive circuit, and these are formed on a transparent glass substrate 28.
In order to make this TFT array into a liquid crystal panel, it is necessary to apply polyimide or the like as an alignment film and perform alignment treatment. However, due to static electricity generated in this treatment, static electricity from the human body, etc. As a measure against a high voltage applied to the insulating film between the data buses, Japanese Patent Laid-Open Publication No. Sho-6
In Japanese Patent Laid-Open No. 1-88557, all gate buses and all source buses in a TFT array are electrically connected in advance to have the same potential, and after a desired panel is completed, the gate buses and data buses are electrically separated. A method is disclosed. The method will be described below.

FIG. 6 shows a conventional example of Japanese Patent Laid-Open No. 61-88.
FIG. 5 is a plan view of a main part of a thin film transistor array in Japanese Patent No. 557, which will be described with reference to this figure.

First, gate buses 29-1, 29-2, ... Are formed of a metal such as Cr on a glass substrate. The gate buses 29-1, 29-2, ... Have almost the same potential because they are all connected by electrodes 30-1, 30-2 ,. Next, silicon nitride, which is a gate insulating film, and then amorphous silicon, which is a semiconductor layer, are continuously formed on the entire surface of the substrate by a plasma CVD method, and the amorphous silicon is patterned into a predetermined shape 33. The silicon nitride is etched to form the contact holes 32. Next, a metal such as Al is selectively deposited and patterned to form the source electrode 36 and the drain electrode 37.

In this state, the gate buses 29-1, 2
9-1, ... And source buses 34-1, 34-2 ,.
Are electrodes 30-1, 30-2, ... And 35-1, 35.
-2, ... Are all connected to the interconnection lines 31, 38, respectively, so that they have almost the same potential, and the gate buses 29-1, 29-2 ,.
.. are connected through contact holes through the respective electrodes, so that all the gate lines and the source lines eventually have substantially the same potential.

Next, although not shown, the pixel electrode is formed by ITO, for example, in such a shape as to be connected to the drain.

In order to use this TFT array substrate as a liquid crystal display element, an alignment film such as polyimide is applied and alignment treatment (rubbing) is performed. The static electricity generated by this treatment or static electricity from the human body is applied. Since all the gate buses and the source buses have the same potential, the reliability against electrostatic breakdown is improved.

After the assembly process of aligning and injecting liquid crystal, the liquid crystal panel is cut by cutting along the cutting lines 39, 40 or by selectively etching so that the respective gate buses and source buses are separated. Complete.

[0011]

However, in the above configuration, when cutting along the cutting lines 39 and 40,
It has no effect on static electricity at the time of cutting, and when it is separated by etching, the structure is such that the metal is exposed at the end surface, so depending on the drying method after etching, moisture remains and the metal corrodes. there is a possibility. Further, even if it is sufficiently dried, it will not be said to have sufficient reliability since it will cause the same problem after being put on the market and placed in a humid environment.
Further, if over-etching is performed too much, there is a problem that an overhang occurs, a crack is formed in the upper insulating layer and disconnection occurs, or the overhang portion breaks to cause dust.

In view of the above point, the present invention has an object to provide a thin film transistor array having a countermeasure against static electricity and having high reliability and yield, a manufacturing method thereof and a manufacturing method of a liquid crystal display device.

[0013]

Means for Solving the Problems A gate bus line and a source bus line are previously formed with a conductive layer capable of anodizing to form a connection portion and have the same potential, and the connection portion is anodized to perform insulation isolation. Make it possible.

In addition, a first substrate having a thin film transistor array in which a gate bus line and a source bus line are previously formed with a conductive layer capable of anodizing to form a connection portion on one main surface and have the same potential, and on one main surface. In a liquid crystal display device in which a liquid crystal material is sandwiched between second substrates having transparent electrodes, and a polarizing plate is disposed on at least one of the both substrates, the connection part of the thin film transistor array is anodized after completion of the liquid crystal display device. Isolate and separate.

[0015]

When the present invention is manufactured by the above-described structure or by the above-mentioned method, not only can electrostatic discharge damage be prevented in the manufacturing process of the thin film transistor array and the manufacturing process of the liquid crystal display device, but also the substrate is necessarily cut to separate each bus wiring. Since it is not necessary, it is possible to prevent the electrostatic breakdown accompanying it. In addition, since the metal is not exposed at the end face when insulation is separated by anodic oxidation, a thin film transistor array or a liquid crystal display device with high yield and reliability can be manufactured.

[0016]

【Example】

(First Embodiment) (FIG. 1) is a plan view of a main part of a thin film transistor array according to a first embodiment of the present invention, which will be described with reference to this drawing.

First, the gate bus wiring 2 and the gate electrode 3 of the TFT are selectively formed on the glass substrate 1 with aluminum, for example. At the same time, a connecting portion 4 for connecting the gate bus wirings is also provided. Then, the gate bus wiring and the gate electrode are anodized. At this time, the connection portion 4 is covered with a resist or the like so as not to be anodized. Next, as a second gate insulating layer, a silicon nitride layer is formed on the entire surface by, for example, a plasma CVD method, and an amorphous silicon semiconductor layer containing almost no impurities serving as a donor or an acceptor is formed on the entire surface. As the protective layer 5, for example, a silicon nitride layer is selectively deposited. And
An amorphous silicon semiconductor layer containing P or As as an impurity serving as a donor or an acceptor is deposited and formed in order to increase ohmic contact between the amorphous silicon semiconductor layer and the second metal layer. It is processed into islands by ordinary photolithography and etching.

Then, as the pixel electrode 6, for example, IT
O a (I ndium- T in- O xide) selectively deposited and formed.

Then, the source bus line 7, the source electrode 8 of the TFT, and the drain electrode 9 of the TFT are selectively formed by depositing aluminum. At the same time, a connection portion 10 for connecting the source bus lines is also provided.

Finally, as a passivation material, silicon nitride is deposited on the entire surface by, for example, a plasma CVD method,
Openings 11 and 12 are provided at the ends of the source bus line and the gate bus line for electrical connection with an external circuit. At the same time, openings 13 and 14 are also provided in the connection portion 4 of the gate bus wiring and the connection portion 10 of the source bus wiring.

After this, if necessary, the openings 11 and 1 are formed.
By using 2 as a power supply terminal for anodic oxidation, the gate bus wiring and the source bus wiring are insulated and separated by anodizing the aluminum exposed in the openings 13 and 14. However, since aluminum is also exposed on the openings 11 and 12, it is necessary to carefully perform it so that the openings 11 and 12 are not anodized. (Second Embodiment) (FIG. 2) is a schematic view showing a second embodiment of the present invention.
First, the steps up to the step of processing the semiconductor layer into an island shape by ordinary photolithography and etching are performed in the same manner as in the first embodiment. After that, the opening 16 is provided at the end of the gate bus wiring for electrically connecting to the opening 15 and an external circuit.
Are formed by ordinary photolithography and etching. Then, for example, ITO which is a transparent conductive material is selectively deposited as the pixel electrode 6, and at the same time, an electrode 17 for connecting the gate bus wiring to an external circuit is formed through the opening 16 and a source formed later. An electrode 18 is provided for connecting the bus wiring to an external circuit.

Then, the source bus line 7, the source electrode 8 of the TFT, and the drain electrode 9 of the TFT are selectively formed by depositing aluminum. At the same time, the connection portion 10 between the source bus lines is covered with the opening 15 so that the gate bus line and the source bus line have the same potential.

Finally, as a passivation material, silicon nitride is deposited on the entire surface by, for example, a plasma CVD method,
Electrodes 17 and 18 for electrically connecting to an external circuit
Openings 19 and 20 are provided above. At the same time, openings 13 and 14 are also provided in the connection portion 4 of the gate bus wiring and the connection portion 10 of the source bus wiring.

After that, although not shown, if necessary,
Electrodes 17 for connecting the gate bus and the source bus to the outside
And 18 may be used as power supply terminals for anodization, and the aluminum exposed in the openings 13 and 14 may be anodized to insulate the gate bus and source bus lines. In this embodiment, since aluminum is not exposed except for the openings 13 and 14, anodic oxidation can be performed more easily than in the first embodiment.

Although the semiconductor is processed into an island shape in the second embodiment, the electrodes 17 and 1 for electrically connecting the pixel electrode 6, the gate bus wiring and the source bus wiring to an external circuit.
8 is formed after the source / drain wiring, an amorphous silicon semiconductor layer containing P or As as an impurity serving as a donor or an acceptor using the source bus wiring 7, the source electrode 8, the drain electrode 9 and the semiconductor protective layer 5 as a mask. If the amorphous silicon semiconductor layer containing almost no impurities serving as donors or acceptors is etched, the islanding step can be omitted.

Alternatively, the electrodes 17 and 18 for electrically connecting the pixel electrode, the gate bus wiring, and the source bus wiring to an external circuit are formed before the gate insulating layer is formed, and the opening 1 is formed.
At the same time as forming 5 and 16, although not shown, an opening for connecting to the drain electrode on the pixel electrode and an opening on the electrode 18 for electrically connecting the source bus line to an external circuit may be provided. Similarly, the step of islanding the semiconductor layer can be omitted. (Third Embodiment) (FIG. 3) is a schematic view showing a third embodiment of the present invention.
First, an active matrix array is formed by the same method as in the first embodiment. A polyimide resin is applied as an alignment film to both of the above-mentioned active matrix array and the glass substrate 16 having a second transparent conductive layer formed on one main surface, and cured, and then an alignment treatment is performed. This orientation treatment makes an angle of about 90 degrees between the above-mentioned active matrix array and the counter glass substrate 16 having the second transparent conductive layer deposited on one main surface.

As a liquid crystal, for example, a twist nematic liquid crystal is sealed between both substrates, and polarizing plates are arranged above and below.

Finally, as in the first embodiment, the aluminum exposed in the openings 13 and 14 is anodized to insulate the gate bus wires and the source bus wires from each other, thereby completing the liquid crystal panel. It (Fourth Embodiment) Although not shown in the drawings in the fourth embodiment of the present invention, an active matrix array is formed by the same method as in the second embodiment. A polyimide resin is applied as an alignment film to both of the above-mentioned active matrix array and the glass substrate 16 having the second transparent conductive layer formed on one main surface, and the polyimide resin is cured, and then an alignment treatment is performed. This orientation treatment makes an angle of about 90 degrees between the above-mentioned active matrix array and the counter glass substrate 16 having the second transparent conductive layer deposited on one main surface.

As the liquid crystal, for example, a twist nematic liquid crystal is sealed between both substrates, and polarizing plates are arranged above and below.

Finally, similarly to the second embodiment, the aluminum exposed in the openings 13 and 14 is anodized to insulate the gate bus lines and the source bus lines from each other, thereby completing the liquid crystal panel. It

Although aluminum is used as the anodizable conductive layer in the above-described first to fourth embodiments, any material that can be anodized can be used. For example, a metal containing aluminum as a main component can be used. Needless to say, tantalum or a metal containing tantalum as a main component may be used.

Further, although the thin film transistor array using amorphous silicon is used in the first to fourth embodiments,
This is not limited to the thin film transistor array using amorphous silicon, and any thin film transistor array using polycrystalline silicon, single crystal silicon, compound semiconductor or the like may be used.

[0033]

As described above, according to the present invention, it is possible to manufacture a thin film transistor array and a liquid crystal display device which can not only prevent electrostatic breakdown but also have a high yield and high reliability. Is very large.

[Brief description of drawings]

FIG. 1 is a plan view of a main part of a first embodiment of a thin film transistor array according to the present invention.

FIG. 2 is a plan view of a principal part of a second embodiment of the thin film transistor array according to the present invention.

FIG. 3 is a schematic diagram in a third embodiment of the method of manufacturing a liquid crystal display device according to the present invention.

FIG. 4 is a schematic diagram in a third embodiment of the method for manufacturing a liquid crystal display device according to the present invention.

FIG. 5 is an equivalent circuit diagram of a liquid crystal display device.

FIG. 6 is a configuration diagram of an active matrix array using thin film transistors as an active matrix array for liquid crystal display.

FIG. 7 is a plan view of a main part of a conventional thin film transistor array having a countermeasure against static electricity.

[Explanation of symbols]

1 glass substrate 2 gate bus wiring 3 gate electrode 4 gate bus interconnection line 5 semiconductor protective layer 6 pixel electrode 7 source bus wiring 8 source electrode 9 drain electrode 10 source bus interconnection line 11 for connecting the gate bus to an external circuit Opening 12 Opening for connecting the source bus line to an external circuit 13 Opening 14 for anodizing and insulating between gate bus lines 14 Opening 15 for anodizing and insulating between source bus lines 15 Gate Opening for connecting bus wiring and source bus wiring 16 Counter glass substrate 17 Connection electrode for external circuit of gate bus 18 Connection electrode for external circuit of source bus 19 Opening of electrode for connection external circuit of gate bus 20 Source Opening of the connection electrode to the external circuit of the bus 21 Scanning signal line 22 Video signal line 23 Thin film transistor (TFT) 24 Liquid crystal cell 25 Pixel electrode 26 Electrode for connecting scanning signal line to external drive circuit 27 Electrode for connecting video signal line to external drive circuit 28 Transparent glass substrate 29-1, 29-2, 29- 3 Gate Bus 30-1, 30-2, 30-3 Connection Electrode to Gate Bus External Circuit 31 Gate Interconnect Line 32 Contact Hole 33 Amorphous Silicon Layer 34-1, 34-2 Source Bus 35-1, 35-2 Connection Electrode to External Circuit of Source Bus 36 Source Electrode 37 Drain Electrode 38 Source Interconnection Line 39 Cutting Line 40 Cutting Line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Kawamura 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yutaka Miyata, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] 1. A thin film transistor array in which at least a gate bus line, a gate electrode, a gate insulating layer, a source bus line, a source electrode, a drain electrode, and a device driving electrode are arranged in an array on a substrate. A thin film transistor array, characterized in that the connection part is formed in advance by a conductive layer capable of anodizing and is made to have the same potential. 2. The thin film transistor array according to claim 1, wherein the anodizable conductive layer is made of a metal containing aluminum or tantalum as a main component. 3. A method of manufacturing a thin film transistor array, comprising the step of anodizing the connection portion of the thin film transistor array according to claim 1 to insulate and separate. 4. A liquid crystal material is sandwiched between a first substrate having the thin film transistor array according to claim 1 on one main surface and a second substrate having a transparent electrode on one main surface, and at least one of the both substrates. A method for manufacturing a liquid crystal display device, characterized in that, on one side, in a liquid crystal display device in which a polarizing plate is arranged, the step of anodizing the connection portion of the thin film transistor array to insulate and separate.