JPS6239065A - Amplification-gate-type thyristor - Google Patents
Amplification-gate-type thyristorInfo
- Publication number
- JPS6239065A JPS6239065A JP17757585A JP17757585A JPS6239065A JP S6239065 A JPS6239065 A JP S6239065A JP 17757585 A JP17757585 A JP 17757585A JP 17757585 A JP17757585 A JP 17757585A JP S6239065 A JPS6239065 A JP S6239065A
- Authority
- JP
- Japan
- Prior art keywords
- thyristor
- region
- main
- oxide film
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000003321 amplification Effects 0.000 abstract description 9
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 9
- 238000002955 isolation Methods 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract 4
- 238000000034 method Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7428—Thyristor-type devices, e.g. having four-zone regenerative action having an amplifying gate structure, e.g. cascade (Darlington) configuration
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はＧａｔｅ感度が５０μＡ程度ｄｖ／ｄｔ特性＞
２００Ｖ／μｓｅｃを保証しソフトスタート回路等に
使用する汎用サイリスタに関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention has a gate sensitivity of about 50 μA dv/dt characteristics>
This invention relates to a general-purpose thyristor that guarantees 200V/μsec and is used in soft start circuits, etc.
サイリスタの使用方法としてはランプ点灯時における初
期トリガ位相を遅らせて導通角を小さくし、暫時この導
通角を拡げていき、突入電流のピーク値を押える調光制
御方式に利用されている。Thyristors are used in a dimming control system that reduces the conduction angle by delaying the initial trigger phase when lighting the lamp, and then temporarily widens the conduction angle to suppress the peak value of the rush current.
これに適用するサイリスタは前述の規格値を満足するＩ
ＯＡ級が主であるが、その構造を第２図によって形成す
る。第２図（ａ）に示すようにＰを約１０１０１４ａｔ
ｏ／ｃｃ含有したＮ導電型Ｓｉ半導体基板（２０）を用
意し、その両面に酸化膜を被覆しその所定位置即ちアイ
ソレイション領域を形成する場所に開口を設け、こ＼か
らＢを導入して５−７ Ｘ １０”ａｔｏｍｓ／ＣＣの
表面濃度をもつアイソレイション領域（２１）を形成す
る。The thyristor used for this purpose satisfies the standard values mentioned above.
The OA class is the main type, and its structure is shown in Figure 2. As shown in Figure 2(a), P is approximately 101014at
An N-conductivity type Si semiconductor substrate (20) containing o/cc is prepared, both surfaces of which are coated with an oxide film, an opening is formed at a predetermined position, that is, a location where an isolation region is to be formed, and B is introduced through this. Form an isolation region (21) with a surface concentration of 5-7 x 10"atoms/CC.
次に、半導体基板（２０）の−主面に被着した前記酸化
膜部分を剥離してＰを導入して表面濃度５〜７ Ｘ １
０”ａｔｏ＋ｍｓ／ｃｃ程度をもつアノード領域（２２
）を形成し第２図に示すようにアイソレイション領域と
接続する。このサイリスタでは主ならびに副サイリスタ
を設け、このベース領域内に形成する二ミッタ領域のｘ
Ｊを変えることによって両サイリスタのＩＯ？特性にバ
ランスを持たせている。Next, the oxide film portion deposited on the main surface of the semiconductor substrate (20) is peeled off and P is introduced to give a surface concentration of 5 to 7×1.
Anode area (22
) is formed and connected to the isolation region as shown in FIG. In this thyristor, a main and a sub thyristor are provided, and the x
IO of both thyristors by changing J? Balanced characteristics.
具体的にはアノード領域（２２）の反対側に位置する半
導体基板表面に被着した酸化膜−二のアノード領域（２
２）の形成後すべて新しい酸化膜にかえる−の所定位置
を開口して主サイリスタ（２３）ならびに副サイリスタ
（２４）のベース領域（２５） （２６）として。Specifically, the second anode region (22) is an oxide film deposited on the surface of the semiconductor substrate located on the opposite side of the anode region (22).
After the formation of 2), the entire oxide film is replaced with a new oxide film by opening at predetermined positions to serve as the base regions (25) and (26) of the main thyristor (23) and the sub-thyristor (24).
Ｂを導入して５ Ｘ １０”ａｔｏｍｓ／ｃｃ程度の表
面濃度とする。B is introduced to a surface concentration of about 5×10”atoms/cc.
次にエミッタ領域の形成に移るが、前述のように前工程
により汚染された酸化膜を新酸化膜としてから所定位げ
に開口を設けてからｎ出したベース領域（２５） （２
６）内にＰを導入して表面濃度をぼゾロ Ｘ １０”ａ
ｔｏｍｓ／ｃｃとしてエミッタ領域（２７） （２８）
を設けるが主サイリスタのエミッタ領域（２７）のｘｊ
を２０μｍ副サイリスタのエミッタ領域（２８）のＸｊ
を１０μｍとする。副サイリスタ（２４）には増幅ゲー
ト（２９）を設けて、ベース領域（２６）にオーミック
接触して設けるゲート電極（３０）からの入力信号を伝
播する。Next, we move on to forming the emitter region. As mentioned above, the oxide film contaminated in the previous process is used as a new oxide film, an opening is formed at a predetermined position, and then the base region (25) (2
6) Introduce P into the surface to lower the surface concentration.
Emitter region (27) (28) as toms/cc
xj of the emitter region (27) of the main thyristor
Xj of the emitter region (28) of the 20 μm sub-thyristor
is 10 μm. The sub-thyristor (24) is provided with an amplification gate (29) to propagate an input signal from a gate electrode (30) provided in ohmic contact with the base region (26).
この増幅グー）−（２９）は公知のように、副サイリス
タ（２４）のベース領域（２６）に形成するエミッタ領
域（２８）と主サイリスタ（２３）のベース領域（２５
）の両表面部分を導電性金属ＡＱによって橋絡して形成
する。このようにしてＩＯＡクラスの増幅ゲート型サイ
リスタを形成するが、主サイリスタのエミッタはいわゆ
る５ｈｏｒｔｅｄ Ｅｍｉｔｔｅｒ構造とし副サイリス
タＮｏｎ ５ｈｏｒｔｅｄ Ｅｍｉｔｔｅｒ構造とする
。As is well known, this amplification group (29) is defined by the emitter region (28) formed in the base region (26) of the sub-thyristor (24) and the base region (25) of the main thyristor (23).
) is formed by bridging both surface portions with a conductive metal AQ. In this way, an IOA class amplification gate type thyristor is formed, but the emitter of the main thyristor has a so-called 5-shorted emitter structure, and the sub-thyristor has a non-5-shorted emitter structure.
この主副サイリスタを持ったサイリスタのｄｖ／ｄｔ特
性は副サイリスタによって規正されるが、ＩＱＴバラン
スはエミッタ領域のＸｊを変えることによって達成して
いる。しかしこの主サイリスタのＩＯＴが１００■Ａ以
上になるとその注入効率が低下しひいてはＶ、が悪化す
る６又副サイリスタの王。Ｔが２００μ八以上になると
そのターンオン時間が長くなり、両サイリスタのラッチ
ング特性も悪くなる等の欠点がある。The dv/dt characteristics of a thyristor having this main and sub thyristor are regulated by the sub thyristor, but IQT balance is achieved by changing Xj of the emitter region. However, when the IOT of this main thyristor exceeds 100 A, its injection efficiency decreases, which in turn deteriorates V, the king of six-pronged sub-thyristors. When T is 200 μ8 or more, the turn-on time becomes long and the latching characteristics of both thyristors deteriorate.
本発明は上記欠点を除去した新規な増幅ゲート型サイリ
スタを提供する６
〔発明の概要〕
本発明では上記目的を達成するため主副サイリスタ領域
濃度に相違をもたせることによってＩＣＩＦのバランス
を採り、更に両エミッタ領域＆よ同時形成によって工程
短縮を図ると共にこのノ（ランス達成を従来より確実に
する手法を採用した。The present invention provides a novel amplification gate type thyristor that eliminates the above-mentioned drawbacks.6 [Summary of the Invention] In order to achieve the above-mentioned object, the present invention balances the ICIF by providing a difference in the concentration of the main and sub-thyristor regions. In addition to shortening the manufacturing process by simultaneously forming both emitter regions, we adopted a method to achieve this balance more reliably than before.
第１図（ａ）〜（シ）により本発明を詳述する。 The present invention will be explained in detail with reference to FIGS.
アノード領域形成までは従来例と同様であるので重複す
るがそのま一記載する。Ｐを約１０”ａｔｏ瓢Ｓ／ｃｃ
含有したＮ導電型Ｓｉ半導体基板■を準備し、その両面
に常法に従って酸化膜を被覆し、アイソレイション領域
形成予定位置を開口してと−からＢを導入して５〜７
Ｘ １０”ａｔｏ＋ｍｓ／ｃｃの表面濃度をもつアイソ
レイション領域■を形成する。The process up to the formation of the anode region is the same as that of the conventional example, so it will be described in its entirety although it will be redundant. P about 10”ato S/cc
Prepare an N-conducting type Si semiconductor substrate (1), coat both sides with an oxide film in accordance with a conventional method, open the position where the isolation region is to be formed, and then introduce B from -5 to 7.
An isolation region (2) with a surface concentration of X 10"ato+ms/cc is formed.
次に、この工程で汚染した酸化膜を剥離して絶粋な酸化
膜を半導体基板ωに形成するが後述する各工程毎にもこ
の新酸化膜形成が実施されることを付記する。Next, in this step, the contaminated oxide film is peeled off to form a pure oxide film on the semiconductor substrate ω, but it should be noted that this new oxide film formation is also carried out in each step to be described later.
この半導体基板のアノード領域形成予定位置である。一
方主面に被着したこの新酸化膜を除去してからＢを導入
して表面濃度５〜７．ｘ１０°ａｔｏｍｓ／ＣＣをもつ
アノード領域（３）を設けると共にアイソレイション領
域と接続する。この状態は第２図と全く同様である。This is the planned position where an anode region will be formed on this semiconductor substrate. On the other hand, after removing this new oxide film deposited on the main surface, B is introduced to achieve a surface concentration of 5 to 7. An anode region (3) with x10° atoms/CC is provided and connected to the isolation region. This state is exactly the same as that shown in FIG.
次いで、アノード領域■と反対側の半導体基板■の他方
主面に被着した酸化膜部分を除去してから主サイリスタ
（イ）ならびに副サイリスタ■のベース領域■■をＰの
導入によって形成する。Next, after removing the oxide film portion deposited on the other main surface of the semiconductor substrate (2) opposite to the anode region (2), the base region (2) of the main thyristor (1) and the sub-thyristor (2) is formed by introducing P.
この場合副サイリスタ■のベース領域■の形成は１０８
０℃でＰを導入し続いて主サイリスタに）のベース領域
■は１０００℃で実施するので、この後者の導入時には
副サイリスタ■のベース領域■にも外方拡散によってＰ
が付着するが、その導入時の温度より低いために表面濃
度には影響を与えない。In this case, the formation of the base region ■ of the sub-thyristor ■ is 108
Since P is introduced at 0°C and then the base region (2) of the main thyristor (2) is carried out at 1000°C, when the latter is introduced, P is also introduced into the base region (2) of the sub-thyristor (2) by outward diffusion.
However, since the temperature is lower than that at the time of introduction, it does not affect the surface concentration.
このＰ導入によって得られるベース領域■■の表面濃度
は副サイリスタ■で約５ Ｘ １０”ａｔｏｍｓ／ｃｃ
、主サイリスタ■で３ Ｘ １０１７ａｔｏ醜ｓ／ｃｃ
位であるにのベース領域形成後エミッタ領域（ａＯ）の
形成に移るが、従来例と異なり同時導入により等しいＸ
Ｊとする。尚ベース領域０■のＸＪは共に４５Ｉｍ位で
ありこのエミッタ領域■０はＰの表面濃度６ＸＩＯ”ａ
ｔｏｍｓ／ｃｃ程度とする。尚主サイリスタのエミッタ
領域（８）は第１図（ｉ）に示したように５ｈｏｒｔｅ
ｄ ｅｍｉ−ｔｔｅｒ構造とするために複数のエミッタ
領域（８）・・・を形成し、二Ｓに導電性金属ＡＱを堆
積してエミッタ電極（１０）を形成するが、副サイリス
タ■はＮｏ＠５ｈｏｒｔｅｄ ｅｍｉｔｔｒｅｒ構造と
する。しかし、そのベース領域■に形成するエミッタ領
域■と主サイリスタに）のベース領域■との両表面部分
に導電性金属ＡＱを堆積して増幅ゲート（１１）とする
。The surface concentration of the base region ■■ obtained by introducing this P is approximately 5 x 10"atoms/cc in the sub-thyristor ■
, main thyristor ■ 3 x 1017ato ugly s/cc
After forming the base region, the emitter region (aO) is formed.
Let it be J. Note that the XJ of the base region 0 is both about 45Im, and the surface concentration of P in the emitter region 0 is 6XIO"a.
approximately toms/cc. The emitter region (8) of the main thyristor is 5horte as shown in Fig. 1(i).
In order to form a demi-tter structure, a plurality of emitter regions (8)... are formed, and a conductive metal AQ is deposited on the 2S to form an emitter electrode (10). It has a 5-horted emitter structure. However, a conductive metal AQ is deposited on both surfaces of the emitter region (2) formed in the base region (1) and the base region (2) of the main thyristor (2) to form an amplification gate (11).
更に、この副サイリスタのベース領域■にはオーム接触
したゲート電極（１２）を設け、アノード領域■にも導
電性金属を被着してアノード電極（１３）を形成して増
幅ゲート型サイリスタを完成する。Furthermore, a gate electrode (12) in ohmic contact is provided on the base region (■) of this sub-thyristor, and a conductive metal is also deposited on the anode region (■) to form an anode electrode (13), completing the amplification gate type thyristor. do.
このサイリスタでは導電型の異なる４半導体層を交互に
配置して半導体基板とし、その一方頂面をＰ導電型層の
アノード領域とし、更に他方頂面に露出したＰ導電型の
ベース領域とＮ導電型のエミッタ領域によって主サイリ
スタならびに副サイリスタを構成することになる。In this thyristor, four semiconductor layers of different conductivity types are arranged alternately to form a semiconductor substrate, one top surface of which serves as an anode region of a P conductivity type layer, and a base region of P conductivity type exposed on the other top surface and an N conductivity type layer. The emitter region of the mold constitutes a main thyristor and a sub-thyristor.
本発明に係る増幅ゲート型サイリスタでは副サイリスタ
のベース表面濃度を主サイリスタのそれより１桁以上高
くしているのでＩ。Ｔを５０μ八程度とし、しかもサイ
リスタとしてのｄｖ／ｄｔ特性を損わなくて済む。しか
もこの両表面濃度の相違によって主サイリスタの１゜Ｔ
を１５＋ａＡ前後に保持され、ＩＯＴのバランスが維持
される。更に、両エミッタ領域は同時に形成してそのＸ
ｊも等しくするため大幅な工程短縮をもたらし、ｃｏｓ
ｔ ｄｏνｎが達成される。In the amplification gate type thyristor according to the present invention, the base surface concentration of the sub-thyristor is made one order of magnitude higher than that of the main thyristor. T can be set to about 50μ8 without impairing the dv/dt characteristics as a thyristor. Moreover, due to this difference in concentration on both surfaces, the main thyristor's 1°T
is maintained at around 15+aA, and the balance of IOT is maintained. Furthermore, both emitter regions are formed simultaneously and their X
Since j is also made equal, the process is significantly shortened, and cos
t dovn is achieved.
この丁ａ丁のバランス維持に伴って、従来例で発生する
副サイリスタにおけるターンオン特性及びラッチング特
性悪化と、主サイリスタでの順方向降下特性劣化を防止
して、長期にわたり増幅型サイリスタの機能を発揮でき
る。By maintaining this balance, the deterioration of the turn-on and latching characteristics of the sub-thyristor and the deterioration of the forward drop characteristics of the main thyristor, which occur in conventional examples, are prevented, and the function of the amplifying thyristor is maintained over a long period of time. can.
【図面の簡単な説明】
第１図（ａ）〜（ｉ）は本発明の詳細な説明する各工程
毎の断面図、第２図（ａ）〜（ｇ）は従来の増幅ゲート
型サイリスタの工程毎断面図である。[BRIEF DESCRIPTION OF THE DRAWINGS] Figures 1(a) to (i) are cross-sectional views of each process to explain the present invention in detail, and Figures 2(a) to (g) are of a conventional amplification gate type thyristor. It is a sectional view for each process.
Claims (1)
導体基板の一方の頂面を陽極とし、他方頂面に露出する
導電型の異なる領域により形成する主サイリスタならび
に副サイリスタを備えるサイリスタにおいて、副サイリ
スタのベース表面濃度を主サイリスタのそれより１桁以
上高くしこのベース領域に形成するエミッタ領域と主サ
イリスタのベース領域とを短絡することを特徴とする増
幅ゲート型サイリスタ。A thyristor comprising a main thyristor and a sub-thyristor formed by an anode on one top surface of a semiconductor substrate obtained by alternately arranging four semiconductor layers of different conductivity types, and regions of different conductivity types exposed on the other top surface, An amplified gate type thyristor characterized in that the base surface concentration of the sub-thyristor is made one order or more higher than that of the main thyristor, and the emitter region formed in this base region is short-circuited with the base region of the main thyristor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17757585A JPS6239065A (en) | 1985-08-14 | 1985-08-14 | Amplification-gate-type thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17757585A JPS6239065A (en) | 1985-08-14 | 1985-08-14 | Amplification-gate-type thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6239065A true JPS6239065A (en) | 1987-02-20 |
Family
ID=16033367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17757585A Pending JPS6239065A (en) | 1985-08-14 | 1985-08-14 | Amplification-gate-type thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6239065A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0312088A2 (en) * | 1987-10-16 | 1989-04-19 | Kabushiki Kaisha Toshiba | Sensitive thyristor having improved noise-capability |
| EP0341730A2 (en) * | 1988-05-13 | 1989-11-15 | Kabushiki Kaisha Toshiba | Gate-controlled bidirectional semiconductor switching device |
-
1985
- 1985-08-14 JP JP17757585A patent/JPS6239065A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0312088A2 (en) * | 1987-10-16 | 1989-04-19 | Kabushiki Kaisha Toshiba | Sensitive thyristor having improved noise-capability |
| EP0341730A2 (en) * | 1988-05-13 | 1989-11-15 | Kabushiki Kaisha Toshiba | Gate-controlled bidirectional semiconductor switching device |
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