JPS63288064A - Composite thyristor - Google Patents

Abstract

PURPOSE:To prevent thyristor operation by the parasitic effect of an IGBT, and to enable a composite thyristor having stable characteristics by forming a mechanism shortening the diffusion length of minority carriers in a drain region in a bipolar type insulated gate field-effect transistor (IGBT) into the drain region. CONSTITUTION:A P-type semiconductor substrate 21 is prepared, an N<-> epitaxial layer 24b is laminated, and an impurity is diffused selectively to the N<-> epitaxial layer to shape an N<+> buried region 50. Epitaxial layers 24c laminated twice onto the P-type substrate through vapor growth are formed, and a P-type isolation region 32 for element isolation is shaped. A main thyristor and an IGBT are formed to the N<-> epitaxial layers 24c. That is, P base regions 23 in the main thyristor and N emitter regions 22 having short-circuit emitter structure divided into the plural are diffused and shaped. A gate oxide film 30 and a gate electrode 29 for the IGBT are formed, a P body region 23a and an N source region 22a are shaped through double diffusion, using the gate oxide film 30 and the gate electrode 29 as masks, and lastly an electrode wiring and an insulating film for protection, etc., are formed.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention provides a bipolar insulated gate field effect transistor (I n5lJlatedGate
Bipolar Transister, I
It is installed between a composite thyristor in which the thyristor (GBT) is installed in parallel, and is particularly used in the structure for preventing the abnormal latch-ab phenomenon of IGBT. Note that the bipolar insulated gate field effect transistor is sometimes called a conductivity modulated MO8FET, and there is no generally accepted Japanese name for it.
It is abbreviated as IGBF.

<Prior art> Compact thyris 9 (T O
220A B Outer St) High sensitivity is required for miniaturization. In general, a small thyristor, for example, the average forward current I T
(AV) When the gate trigger current IGT is several tens of μA, the critical off-voltage increase rate dV/dt is 0.0. I
Similarly, when G- is opened, dV/dtton 1
000V,! : In this case, I GV≧several 10 mA. In other words, if you try to improve sensitivity by reducing IGT, d
It has contradictory characteristics that V/dt decreases.

Currently, amplification gate thyristors, MOS gate thyristors, and the like are being devised to improve the trade-off between IGT and dV/dt. Below, these elements will be explained.

A general schematic cross-sectional view and an equivalent circuit diagram of an amplification gate thyristor are shown in FIGS. 4 and 5, respectively.

The amplification gate thyristor has a main thyristor h1 and an auxiliary thyristor 1h2 arranged side by side on one semiconductor substrate 1, and the gate electrode of the main thyristor and the cathode electrode of the auxiliary thyristor are integrally connected by a wiring machine ejl18. The main thyristor Th1 has a P emitter region 5, an N-base region 4, a P base region 3, an N-emitter region 2, and the auxiliary thyristor Th2 has a P emitter region 5, an N-base region 4,
Each of them is composed of a P base region 3 and an N emitter region 2a. When a voltage Vo is applied between the anode electrode 6 and the cathode electrode 7, and a gate current Ip is applied to the gate electrode 1, the gate electrode 9, and the cathode electrode 7, the auxiliary thyristor Th
2 is fired, the on-current (emitter'IB flow) IE of the auxiliary thyristor h2 flows into the gate of the main thyristor Til1, and the main thyristor is fired. Normally main thyristor gate trigger current I GT and auxiliary thyristor I
E+ has a relationship of IGT<IE, which causes a so-called overdrive, which promotes the expansion of the firing region of the main thyristor, resulting in a high sensitivity and high @W-on-N flow rate of rise di/dt.
Can you get it? However, if the auxiliary thyristor is made highly sensitive, the dV/dH of the amplification gate thyristor depends on the dV/dt of the auxiliary thyristor, so the dV/dH of the amplification gate thyristor becomes too high.
There is a problem that V/dt cannot be obtained.

Next, a general schematic cross-sectional view and an equivalent circuit of a MOS gate thyristor are shown in FIGS. 6 and 7, respectively. In the drawings below, the same reference numerals refer to the same or corresponding parts. In FIG. 6, V is applied between the 7-node Ti electrode 6 and the cathode electrode 17.

Applying a positive voltage of
I! When a positive bias equal to or higher than the gate trigger voltage VGT is applied to lI, an inversion layer is formed in the portion of the P base i region 13 directly below the gate electrode 19, and Ti is transferred from the N-base region 4 through this inversion (2) to the N emitter region 12. The current flows and the main thyristor consisting of P emitter region 5, N-base region 4, P base region 13 and N emitter region 12 fires.
Since the N emitter region 12 and the P space region 13 are short-circuited by the cathode electrode 17, the dV/dt resistant pot is similar to a thyristor with a so-called short emitter structure.

That is, when a zero forward voltage is applied to the anode electrode 6 and the cathode electrode 17, the displacement current 1p generated at the junction J between the N-base region 4 and the P-base region 13, and the The product of region 13 and intersection resistance R is V
If ev is not present* (VGT > I pXR), the thyristor does not fire and remains in the blocking state. Therefore, in order to improve dV/dt, it is necessary to increase the short-circuit ratio between the N emitter region 12 and the P base region 13. The problem with the structure of this MOS gate thyristor is that due to the increased short-circuit ratio between the N emitter region 12 and the P base region 13, the conduction region spreads poorly and the di/dt characteristics deteriorate (about several hundred A/d).
μS), and the effective area of the N emitter region 12 decreases, resulting in an increase in chip size.

In order to solve the above problems, we recently applied for patent application No. 6l-179.
A composite thyristor according to 832N was proposed.

As shown in FIG. 8, this composite thyristor includes a main thyristor Th1 with a short-circuited emitter structure and a bipolar insulated gate field effect transistor IGBr on one semiconductor substrate 21.
are installed in parallel, and the main thyristor's P base region t423 and IG
The N source region 22a of the BT is connected to the wiring electrode film 28.

When a forward voltage Vo is applied to the anode electrode 26 and the cathode electrode 27, and a gate trigger voltage V, 11 is applied to the gate electrode 29, the rGBT turns on, and its on-current flows to the wiring electrode 1.
! P base f! of main thyristor Th1 through 28. '! [
23 as a gate current, and the main thyristor Th1 is fired. Since the dV/dt resistance of IGBr is sufficiently larger than that of the auxiliary thyristor of the amplification gate thyristor, dV/(
ltft4fil is improved. In addition, since the gate of IGBT has a MOS structure and has high impedance characteristics and high conductivity characteristics, the composite thyristor at the mouth has high sensitivity and has a low dl/
dt characteristics are improved. IGBTs can control large currents with low power and have low on-state voltages.

(Problems to be Solved by the Invention) As mentioned above, the composite thyristor in which the IGBI is installed in parallel with the main thyristor has high sensitivity, and the dV/dt and dr/dt
Properties are also improved. However, the IGBT may operate as a thyristor due to parasitic effects, which poses a problem.

The purpose of the present invention is to maintain the high sensitivity, high dV/dt, and high dl/dt characteristics of the conventional composite thyristor (shown in Fig. 8), prevent thyristor operation due to parasitic effects of IGBT, and make it more stable. The object of the present invention is to provide a composite thyristor with such characteristics.

[Configuration 1 of the Invention (Means for Solving Problems) The composite thyristor of the present invention has a main thyristor and a bipolar insulated gate field effect transistor (IGBT) arranged side by side on one semiconductor substrate, and a base region of the main thyristor. and I
A conventional composite thyristor in which the source region of the GBr is connected with a conductive material (Japanese Patent Application No. 179832/1983) 2. New (a mechanism for reducing the diffusion length of minority carriers in this region in the drain region of the IGBT) It is a composite thyristor characterized by providing an IGBT structure.
DMO8FE1 or VMOSFE1)+7)
-118 layers of an opposite conductivity type region (referred to as an opposite conductivity type train region for convenience) are added in contact with the first conductivity type drain region, and in the present invention, a diffusion length reduction mechanism is provided in the one conductivity type drain region. It is something that

-The mechanism for reducing the diffusion length of minority carriers provided in the sN-type drain region is a buried region of one conductivity type with a concentration, diffusion of gold, platinum, or lead that serves as a recombination center, or formation of lattice defects by electron beam or neutron irradiation. is the desired real tSS*.

(Function) I G B T C, VD MOS FE-1 (7
) A drain region of one conductivity type is additionally laminated with a drain region of the opposite conductivity type, and the carrier density of the one conductivity type drain region in the on state is high. The diffusion length reducing RMA provided in the drain region quickly eliminates accumulated carriers during turn-off and improves turn-off characteristics. Also, a parasitic thyristor is formed in the IGBT, which is made up of four layers: a source region of one conductivity type, a body region of the opposite conductivity type, a -SS type drain region, and an additionally laminated drain region of the opposite conductivity type of the VD MOS FET.
The diffusion length reduction mechanism in the drain region of one conductivity type acts to prevent this parasitic thyristor from performing thyristor operation.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of the composite thyristor of the present invention, in which the main thyristor rh1 and (GET) are arranged side by side on one semiconductor substrate 21.

The main thyristor Th1 extends from the first main surface of the substrate 21 to the second main surface on the opposite side, and includes an N emitter region 22, a P base region 23, an N-base region 24, and a P base region 24 in parallel to the main surface.
Emitter regions 25 are laminated to form a short-circuited emitter structure.

Further, the IGBI is provided with an N source region 1a22a and a channel forming portion 23b of a P body region 23a in the surface layer of the first main surface of the substrate 21, and an N-
VD MOS FE with drain region 24a formed
Tt, :)' drain region 25a is added, but in the present invention, the N-drain region hi! A feature is that an N buried region 50 is provided in 24a as a mechanism for reducing the diffusion length of minority carriers (holes) in this region.

Further, the gate electrode 28 of the main thyristor Thl and the source electrode 31 of the IGBT are electrically connected. Sign △,
K and G indicate the anode, cathode, and gate terminals of the composite thyristor, respectively, the main thyristor Th 1 and r
GBr common 7 nodes 71 poles 26, main thyristor Th
It is connected to the cathode terminal 27 of 1 and the gate electrode 29 of rGBT.

N region 14 and body region 23a constitute a Zener diode 1 and are inserted to prevent overvoltage breakdown of gate oxide 130. 11 is a protective oxide film.

FIG. 2 shows an equivalent circuit of the above composite thyristor.

The R discharge in the figure represents the intersection resistance between the N emitter region 22 and the P base region 23.

Next, the operation of this composite thyristor will be explained. A positive voltage Vo is applied between the anode terminal A and the cathode terminal,
Also, a positive bias V G is applied between the gate terminal G and the cathode terminal.
When T is respectively applied, an inversion layer is generated in the channel forming portion 23b directly under the gate electrode 29 of the IGBF, and a channel is formed.

As a result, the IGBT becomes conductive, and an on-current flows from the anode electrode 26 to the source electrode 31.

This on-current is the gate electrode 28 of the main thyristor 1゛h1.
flows into the P base region 23, and the main thyristor fires. Note that the turn-off operation of the IGBT is performed using VDM.
Similar to OS FEI, this is performed by lowering the voltage applied to the gate electrode 29 below the threshold value.

The IGBT includes an N/- body region 22a and a P body region 23.
a, N- drain region 1424a and P drain region 25
A parasitic thyristor is constructed, and it is necessary to prevent this from operating as a thyristor. For this reason, a mechanism that increases the concentration at the intersection between the N source region 22a and the P body region 23a and reduces the diffusion length of minority carriers (holes) in the N-drain region, for example, the N1 buried region, doping with heavy metals that acts as a recombination center. Alternatively, αOne and α are parasitic thyristors that selectively create lattice defects by irradiating electron beams or neutron beams. By reducing p, the occurrence of parasitic thyristor operation is prevented.

Further, in the N-drain region 24a of the IGBT, VDM
Unlike the OS FET, there are excessive minority carriers (holes) injected from the P-train region 25a, which deteriorates the turn-off characteristics, but the N-drain fft region 24
This can be improved by providing a mechanism for reducing the diffusion length of minority carriers in a.

In the structure of the present invention, first, the IGBT is designed using the method described above so that the parasitic thyristor does not operate when the current is below the rated N current. Next, for the main thyristor, the standard value, for example 1. knee! 301A.

Design to obtain dV/dt>1000V/μS IIr.

The N source region 22 of the IGBT is designed so that a source current several times higher than the gate trigger current fGt of the main thyristor flows.
By designing the area of a, the main thyristor can spread the conduction area well by overdriving the gate, resulting in a high d
l/dt can be achieved.

Next, an outline of the method for manufacturing a composite thyristor of the present invention will be explained with reference to FIGS. 3(a) and 3(b). As shown in Figure (a), a P-type semiconductor substrate 21 is first prepared, and the impurity concentration is increased to approximately 1014 to 10'' atoms by vapor phase growth.
/ci' is laminated to a thickness of about 30 μm. Next, an N1 buried region 50 is formed by selectively diffusing impurities at a concentration of 10'98 toms/Cl113 into this N-epitaxial bump. Next, as shown in FIG. 6(b), an N-epitaxial layer having the same concentration as above is deposited by vapor phase growth. The height of the epitaxial tN24c layered twice on the P-type substrate is 80 to 90 .mu.-. Next, P for element isolation
A mold separation region [32] is formed. Although subsequent steps are not shown, the main thyristor and IGBT are formed in the N-epitaxial layer 240 by a known method. That is, the P base fA1423 of the main thyristor (depth approximately 15 to 20
.mu.m) and a plurality of divided N emitter regions 1a22 (about 5 .mu.m in length) having a short-circuited emitter structure.

Next, a gate oxide film 30 and a gate electrode 29 of the IGBT are formed, and using these as a mask, a P body region 23a and an N source region 22a are formed by double diffusion. Finally, electrode wiring, a protective insulating film, etc. are formed to obtain the composite thyristor shown in FIG. As described above, in this embodiment, N-
N as a mechanism for reducing minority carrier diffusion in the drain region
+Although we have described an example in which a buried region is provided, it is possible to use lifetime killer materials such as Au, Pt%Cu1Ni, etc. as heavy metals when diffusing heavy metals that serve as recombination centers.For example, after forming a diffusion layer, , AU is selectively deposited on the main surface on the P emitter region side and heated and diffused. Further, in the embodiment, a thyristor in which the single conductor type becomes the N type has been described.

[Effects of the Invention] As described above, it is generally difficult to achieve both high sensitivity and high dV/dt durability with an amplification gate thyristor due to the structure of the auxiliary thyristor. Also, in MOS gate thyristor, N emitter mhi! Although it is possible to increase dr/dt by reducing the short circuit ratio between P base region 12 and P base region 13, this results in a decrease in d/dt tolerance.

In the composite thyristor of the present invention, a structure for preventing the thyristor operation of the parasitic thyristor of IGBI', that is, a mechanism for reducing the diffusion length of minority carriers in this region in the drain region of one conductivity type, is provided, thereby preventing the parasitic latch of tGBT. Up phenomenon is prevented and stable high sensitivity (voltage drive!
11) We were able to achieve ila dV/dt tolerance and high dI/dt characteristics. Further, the depth area is equivalent to that of a general amplification gate thyristor and can be smaller than that of a MOS gate thyristor.

[Brief explanation of the drawing]

Fig. 1 is a sectional view of the composite thyristor of the present invention, Fig. 2 is its equivalent circuit diagram, Fig. 3 is a sectional view showing the manufacturing process of the composite thyristor of Fig. 1, and Fig. 4 is a sectional view of the conventional amplification gate thyristor. 5 is an equivalent circuit diagram, FIG. 6 is a sectional diagram of a conventional MOS gate thyristor, FIG. 7 is an equivalent circuit diagram thereof, and FIG. 8 is a sectional diagram of a conventional composite thyristor in which IGBTs are arranged in parallel. It is. 21... Semiconductor substrate, 22... One conductivity type emitter region (N emitter region), 22a... One conductivity type source region (N source region), 23... Opposite conductivity type base region 1a (P base 23a...Body region of opposite conductivity type (P body region), 23b...Channel forming portion, 24...Pace region of one conductivity type (N-base region ia), 24a...One conductivity type Type drain region (N-
Drain region It), 25... Emitter region of opposite conductivity type (P emitter region), 25a... Region of opposite conductivity type to be additionally laminated (P drain region 14), 26... Anode electrode, 27... Cathode Electrode, 29... Gate electrode, 30... Gate oxide film, 50... One conductivity type buried region (N+ buried region). Figure 1 Figure 3

Claims (1)

[Claims] 1. In one semiconductor substrate, (a) an emitter region of one conductivity type and a base region of the opposite conductivity type extending parallel to the principal surface from the first principal surface of the substrate to the second principal surface on the opposite side thereof; , a main thyristor formed by laminating a base region of one conductivity type and an emitter region of the opposite conductivity type in this order; and (b) a source region of one conductivity type and a body region of the opposite conductivity type on the surface layer of the first main surface of the substrate. A bipolar type insulated gate vertical field effect transistor having a channel forming portion and a drain region of one conductivity type formed in contact with a body region in the substrate, and an additionally laminated region of an opposite conductivity type in contact with the drain region. In a composite thyristor in which an insulated gate field effect transistor is arranged in parallel and a base region of one conductivity type of the main thyristor and a source region of a bipolar insulated gate field effect transistor are connected by a conductive material, in the drain region of the one conductivity type. A composite thyristor characterized by having a mechanism for reducing the diffusion length of minority carriers in this region. 2. The composite thyristor according to claim 1, wherein a buried region of one conductivity type with a higher impurity concentration is provided in the drain region of one conductivity type as a mechanism for reducing the diffusion length. 3. The composite thyristor according to claim 1, wherein a heavy metal serving as a recombination center is diffused into the drain region of one conductivity type as a mechanism for reducing the diffusion length. 4. The composite thyristor according to claim 1, wherein, as the mechanism for reducing the diffusion length, lattice defects are formed by irradiating the one conductivity type drain region with an electron beam or a neutron beam.