JPS5978530A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5978530A JPS5978530A JP18957282A JP18957282A JPS5978530A JP S5978530 A JPS5978530 A JP S5978530A JP 18957282 A JP18957282 A JP 18957282A JP 18957282 A JP18957282 A JP 18957282A JP S5978530 A JPS5978530 A JP S5978530A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- electrodes
- window
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 150000001875 compounds Chemical class 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 238000000605 extraction Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 9
- 239000007772 electrode material Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- 240000008415 Lactuca sativa Species 0.000 description 1
- 235000003228 Lactuca sativa Nutrition 0.000 description 1
- 241000587008 Pachyphytum oviferum Species 0.000 description 1
- 240000002834 Paulownia tomentosa Species 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011014 moonstone Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）発明の技術分野
本発明は半導体装置の製造方法に係り、特に化合物産導
体装置の電極形成方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming electrodes of a compound-based conductor device.
（ｂ） ｉメＬ来技術と問題点
インジウム・アンチモン（ＩｎＳｂ） 、インジウノ、
り♂ｌｉ （ｌｎＰ ） 、水ａｎ ・ソ用ミウム・テ
ルル（ｌ１ｇＣｄＴｅ）等の化合物半導体装置の電極を
形成するに際し、従来はＣｒ−＾１１＋ Ａｕ、 Ｓｎ
、 Ｉｎ等の金属を用いてオーミックコンタク１−電極
と、これに接続する引出し電極とを形成していた。(b) Next technology and problems Indium antimony (InSb), Injiuno,
Conventionally, when forming electrodes for compound semiconductor devices using materials such as li♂li (lnP), water ann, and mium tellurium (l1gCdTe), Cr-^11+ Au, Sn
, In and other metals were used to form the ohmic contact 1-electrode and the lead-out electrode connected thereto.
（ｊＬ来のかかる製造力７ノモでは、製造工程が繁１９
ｔであるのめならず、上記金属はオーミノダニ１フ２２
１〜月石或いは引出し電極材料として必ずしも適してい
るわりでは゛な＼、良好なオーミック−１ンタク１−と
、機械的強度の優れた引出し電極が得られたとは名い６
！Ｉｔい。ちなめにＳｉの場合、八〇を用いて両要求を
満足出来るが、化合物半導体に対しては良好なメーミン
クコンタク１−を形成する＋」料が、必ずしも機械的強
度に優れ、ワイー・ホンディングが容易な引出し電極材
料という訳ではない。(JL has 7 manufacturing capabilities since then, and the manufacturing process has increased by 19 times.
It is true that the above metal is Ominomite 1F22
Although moonstone is not necessarily suitable as a material for lead-out electrodes, it is said that good ohmic contact and lead-out electrodes with excellent mechanical strength were obtained6.
! It's bad. Incidentally, in the case of Si, both requirements can be satisfied using 80, but for compound semiconductors, materials that form good mechanical contacts do not necessarily have superior mechanical strength and It is not necessarily an easy extraction electrode material.
（ｃ＋ 発明の目的
本発明の目的は上記問題点を解消して、良好なオーミッ
クコンタクトを容易に（ｑることの出来る半導体装置の
製造方法を提供Ｊ゛ることにある。(c+ OBJECT OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device that can easily make good ohmic contact.
＋ｄ） 発明の構成
本発明の特徴は、化合物半導体よりなる被処理基板表面
に所定の絶縁膜を形成する工程と、前記被処理基板の所
定領域上に対応する位置に開口を有するレジスト膜を前
記絶縁膜上に形成する工程と、該レタス１〜膜をマスク
として前記絶縁膜を選択的に除去して前記所定領域上に
コンタクト窓を形成する工程と、前記レジスト膜及び絶
縁膜をマスクとして前記コンタクト窓内に露出せる前記
被処理載板表面に所定の金属膜を形成してコンタクト電
極を形成する工程と、前記レジスト股を除去することに
よりその」二に被着せる前記金属膜を同時に除去する］
二程と、前記コンタクト電極から導出された引出し電極
を形成する工程とを含むことにある。+d) Structure of the Invention The features of the present invention include a step of forming a predetermined insulating film on the surface of a substrate to be processed made of a compound semiconductor, and a step of forming a resist film having an opening at a position corresponding to a predetermined region of the substrate to be processed. a step of forming a contact window on the predetermined region by selectively removing the insulating film using the Lettuce 1 film as a mask, and forming a contact window on the predetermined region using the resist film and the insulating film as a mask; A step of forming a contact electrode by forming a predetermined metal film on the surface of the processing plate exposed in the contact window, and removing the resist crotch to simultaneously remove the metal film deposited on the second surface. ]
and a step of forming an extraction electrode led out from the contact electrode.
（ｅｌ 発明の実施例
以下本発明の一実施例をその製造工程の順に第１図〜第
４図を参照しながら説明する。Embodiment of the Invention An embodiment of the invention will now be described in the order of its manufacturing process with reference to FIGS. 1 to 4.
第１図において、■は化合物半導体よりなる被処理基板
で例えば半絶縁（セミインシｊ−１／−タ）型の Ｉｎ
Ｐ基板、２は拡ｆｌ＆層で例えば硫黄（Ｓ）のようなｎ
型の不純物を導入した層、３は絶縁膜で例えば二酸化シ
リニＪン（５ｉＯ２）膜である。In Fig. 1, ■ is a substrate to be processed made of a compound semiconductor, for example, a semi-insulating (semi-insulating) type In
P substrate, 2 is an expanded fl & layer, such as n such as sulfur (S).
The layer 3 into which type impurities are introduced is an insulating film, for example, a silicon dioxide (5iO2) film.
上記構造はＩｎＰ基板１表面にＳを拡ｔｉ！１．するか
、或いはイオン注入した後加熱処理を施す等の方法によ
り拡１１＆Ｊｉ４２を形成した後、化学気相成長法（Ｃ
Ｖ Ｉ）法）等により ５ｉ０２膜３を形成してｉ）す
られる。In the above structure, S is spread on the surface of the InP substrate 1! 1. Alternatively, after forming the expansion 11&Ji42 by a method such as ion implantation followed by heat treatment, chemical vapor deposition method (C
The 5i02 film 3 is formed by i) method VI) or the like.
次いで第２図に示すように、」二記拡散層２上部に開１
−１４を有するレジスｌ−１１Ｊ ５を上記５ｉ０２脱
３上全而に形成し、これをマスクとして上記５ｉ０２股
３を選択的に除去し、コンタクｌ−窓６を開［］する。Next, as shown in FIG.
A resist l-11J 5 having a diameter of -14 is formed on the entire surface of the 5i02 removed 3, and using this as a mask, the 5i02 crotch 3 is selectively removed, and the contact l-window 6 is opened.
次いで第３図に示すよつに、」−記コノンタクト窓６表
面を含むレジス日美５」二に、被処理基板１即ち Ｉｎ
Ｐ基板１に対して良好なオーミックコンタクトを形成す
る金属、例えばＳｎ或い＆Ｊ金−錫（Ａｕ−５ｎ）を蒸
着θｅ等により被着−１しめる。かくすることにより、
コンタクト窓６内にはコンタク１〜電極７が形成されろ
。このコンタク１−電極７は、５ｉＯｊ１９３及びレジ
スＩ−ＩＢ９５とからなる段差のため、レジストｎ仰５
上に被着したＳｎ或も料；Ｉ：／１ｕ−５ｎ膜）（とは
接続することなく分離して形成される。Next, as shown in FIG.
A metal that forms good ohmic contact with the P substrate 1, such as Sn or gold-tin (Au-5n), is deposited by vapor deposition θe or the like. By doing so,
Contacts 1 to electrodes 7 are formed within the contact window 6. This contact 1-electrode 7 has a resist n height of 5 due to the step formed by 5iOj193 and resist I-IB95.
It is formed separately from the Sn film (I:/1u-5n film) deposited thereon without being connected to it.
次いて第４図に示すように、上記レジスト膜５を除去す
るごとによりその上に被着せるＳｎ或いはΔｕ−５ｎｌ
ｌ＊ ８を同時に除去し、更に上記」ンタクト電４ｆＡ
７を含む５ｉＯ２１１美３上に箪気低Ｔ＞−Ｃが小さく
Ｈ４つ機械的強度の優れた金属３例えばアルミ−ラム（
八Ｑ）を選択的に被着せしめて、コンタク１電極７から
導出された引出し電極９を形成する。Next, as shown in FIG. 4, each time the resist film 5 is removed, Sn or Δu-5nl deposited thereon is
1 * 8 at the same time, and then the above contact voltage 4fA.
5iO211 containing 7, low T>-C low H4 Metal 3 with excellent mechanical strength, such as aluminum ram (
8Q) is selectively deposited to form an extraction electrode 9 led out from the contact 1 electrode 7.
かくして得られた本実施例による平導体装置の完成体は
、コンタクト電撓７と引出し電極９の材料をそれぞれ最
適に選ぶことが出来る。従ってオーミック−ｌンタクト
、導電性、及び機械的強度共に良好な電極配線を形成す
ることが可能である。In the thus obtained completed flat conductor device according to this embodiment, the materials of the contact deflector 7 and the extraction electrode 9 can be selected optimally. Therefore, it is possible to form electrode wiring with good ohmic contact, conductivity, and mechanical strength.
しかもコンタクト窓６とコンタクト電極７との相方４泣
置関係は、」二連の説明により理解される如く自己整合
（セルファライメン１）して決定されるので、極めて高
精度であり、１土−）その製造Ｅｌ−程シ６１非常に節
１口化される。Furthermore, the relative positional relationship between the contact window 6 and the contact electrode 7 is determined by self-alignment (self-alignment 1), as understood from the two-part explanation, so it is extremely accurate and can be done in one place. -) Its manufacturing process is very simple.
なお本発明は上記−実施例に限定されるものではなく、
総ての化合物半導体装置を製造する際に使用し肖ること
は特に説明するまでもないであろう。Note that the present invention is not limited to the above-mentioned examples,
There is no need to specifically explain that it can be used in manufacturing all compound semiconductor devices.
（ｆｌ 発明のジノ果
以上説明した如く本発明によれば、化合物半導体装置の
コンタクト電極と引出し電極とをそれぞれ最適月利をも
って構成することが出来、しかもその！Ｉｆ’Ｊ造工程
は高精度且つ容易となる。(fl) Results of the Invention As explained above, according to the present invention, the contact electrode and lead-out electrode of a compound semiconductor device can be constructed with optimum monthly yield, and the If'J manufacturing process is highly accurate and It becomes easier.
第１図〜第４図は本発明の−・実施例をその時人聞工程
の順に示す要部断面図である。
図において、■は化合物半導体よりなる被処理基板、２
はオーミックコンタクトを形成すべき）す［定の領域、
３は絶縁膜、４は開Ｌ１．５はレジスト１１黄、６は二
１ンタクト窓、７は二ｌンタクト且ｔ＃桐、３（輯金属
股、９は引出し電極を示す。FIGS. 1 to 4 are sectional views of main parts of embodiments of the present invention, showing the steps in the human process. In the figure, ■ is a substrate to be processed made of a compound semiconductor;
should form an ohmic contact)
3 is an insulating film, 4 is an open resist 11, 5 is a resist 11 yellow, 6 is a 21 contact window, 7 is a 21 contact and T# paulownia, 3 is a metal crotch, and 9 is an extraction electrode.
Claims (1)
膜を形成する］−稈と、ｎｊＩ記被処理基根の所定領域
上にり・１応する位置に開口を有するレジン、ト膜を前
記絶縁１１央−４−に形成する工程と、該１７ジスト股
をマスクとして前記絶縁膜を選択的に除去して前記所定
領域上にコンタク１−窓を形成する一＋Ｉ程と、前記レ
ジスト膜及び絶縁膜をマスクとして前記二１ンタクト窓
内に露出・Ｕる前記被処理ＪＩＳ扱表面表面定の金属膜
を形成してコンタクト電極を形成する工程と、前記レジ
スト膜を除去することによりその」−に被着・ける前記
金属りを同時に除去する工程と、前記コンタク［電極か
ら導出された引出し電極を形成する工程とを含むことを
特徴とする半導体装置の製造方法。Processed object made of compound semiconductor! , (Formation of a predetermined insulating film on the plate surface) - A resin film having an opening at a corresponding position is formed on the culm and a predetermined region of the base to be treated. a step of selectively removing the insulating film using the 17 resist crotches as a mask to form a contact window on the predetermined region; 21. A step of forming a contact electrode by forming a metal film on the JIS treated surface to be exposed in the contact window, and a step of depositing on the surface by removing the resist film. A method for manufacturing a semiconductor device, comprising the steps of simultaneously removing metal and forming an extraction electrode led out from the contact electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18957282A JPS5978530A (en) | 1982-10-27 | 1982-10-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18957282A JPS5978530A (en) | 1982-10-27 | 1982-10-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5978530A true JPS5978530A (en) | 1984-05-07 |
Family
ID=16243571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18957282A Pending JPS5978530A (en) | 1982-10-27 | 1982-10-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5978530A (en) |
-
1982
- 1982-10-27 JP JP18957282A patent/JPS5978530A/en active Pending
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