JPS5816569A - Vertical type mosfet - Google Patents
Vertical type mosfetInfo
- Publication number
- JPS5816569A JPS5816569A JP56113713A JP11371381A JPS5816569A JP S5816569 A JPS5816569 A JP S5816569A JP 56113713 A JP56113713 A JP 56113713A JP 11371381 A JP11371381 A JP 11371381A JP S5816569 A JPS5816569 A JP S5816569A
- Authority
- JP
- Japan
- Prior art keywords
- region
- channel
- electrode
- type
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 239000005368 silicate glass Substances 0.000 abstract description 2
- 108091006146 Channels Proteins 0.000 abstract 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 206010011878 Deafness Diseases 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は縦形のＭＯ８ＦＢ’ｌ”に関し、主としてＰチ
ャネルＭＯ８ＦＨＴを対象とする。 １ＮチヤネルＦＥ
Ｔにコンプリメンタリ−（１１補的）に組合せ、又は単
独の素子として大電流のスイッチング動作を行わせる目
的で、しばしばＰチャネル形の電力用ＦＥＴが必要とさ
れている。かかる用途や目的のために電力用の大電流・
高耐圧のＦＩＴを得るには、その特性上、ドレイン電極
が基板となる縦形のＦＥＴが適合している。すなわち、
ＰｉＩ半導体基板の主表面に形成したＮ型ウェルの′一
部にＰ型ソース領域とそ゛の電極及び絶縁ゲートを設け
、基板の裏面よりドレイン電極を取出す”ことにより、
単位面積当りのｌＦ’ＥｉＴ動作する活性面積が大きく
とれ、゛その結果トレーインソース間ノオン抵抗の低減
、相互フンダクダンスの増大、したがって電流容量の増
大といった目的が達せられる”ン本発明の目的はこのよ
うな縦形のＰチャネル電力用ＦＥＴを提供することにあ
る。本発明にＪ：るＰｆ−ｖ＊＃−ＭＯＳＦＥＴは第１
ｗＪ１ｍ＋−（ｇｌで示す各工程のプルセスに従って
製造される。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical MO8FB'l'', and is mainly directed to a P channel MO8FHT. 1N channel FE
P-channel power FETs are often required to perform high current switching operations in complementary combinations or as single devices. For such uses and purposes, large currents and
In order to obtain a high breakdown voltage FIT, a vertical FET whose drain electrode is the substrate is suitable due to its characteristics. That is,
By providing a P-type source region, its electrode, and an insulated gate in a part of an N-type well formed on the main surface of a PiI semiconductor substrate, and taking out a drain electrode from the back surface of the substrate,
The active area in which lF'EiT operates per unit area can be increased, and the objectives of the present invention are to reduce the non-on resistance between the train and the source, increase the mutual fund dance, and therefore increase the current capacity. It is an object of the present invention to provide a vertical P-channel power FET as shown in FIG.
wJ1m+- (manufactured according to the process steps indicated by gl).
（組ま′ず、Ｂ（ボロン）を高濃度にＶ−プ′したＰ＋
撤８１基板１上に低濃度のＰ形エピタキシャル成長層２
を形成したＰ−Ｐ”ｌｉウェハを用意する。（ｂｌこの
ウェハ表面にホトレジス）処理した酸化ＩＨ。(Unassembled, P+ with high concentration of B (boron)
Removal 81 Low concentration P type epitaxial growth layer 2 on substrate 1
A P-P"li wafer is prepared. (photoresist is formed on the surface of this wafer) and treated with IH oxide.
をマスクにして選択的にＮｌ！ＩのＮウェル拡散層３を
形成する。この部分は前記基板に対し部分的に深く存在
させる。１０）Ｌかる後、ゲートとなる部分に熱酸化に
より新たにゲート酸化膜７を形成する。Selectively Nl with a mask! An N well diffusion layer 3 of I is formed. This portion is partially deep to the substrate. 10) After completing the process, a new gate oxide film 7 is formed by thermal oxidation on the portion that will become the gate.
このときＦＩＴの周囲のフィールド部には最初の厚い酸
化膜ｌＯをそのまま歿存させる。ｌｄｌゲートにはポリ
８ｉをデポジットし、ホトレジスト処理によってポリ８
ｉを選択的にエツチング除去することにより形成する。At this time, the initial thick oxide film 1O is left intact in the field area around the FIT. Poly 8i is deposited on the ldl gate, and poly 8i is removed by photoresist processing.
It is formed by selectively etching away i.
この後チャネル形成のためのＮ領域４をイオン打込みと
浅い拡散により選択的に形成する。（ｅ１シかる後にソ
ースとなるべき部分の酸化膜をホトレジスト処理により
エツチングし、Ｐｇ領領域前記ポリ８ｉマスクによるチ
ャネル部形成と同一マスクにて形成する。このときソー
スの真中部分はＰｍ領域を形成することなく、先ｆｊＮ
ｌｌ形成領域を表面酸化膜部分に露出させておくとよい
。（ｆｌこの後本発明の構成に欠くことのできない部分
であるＮｕｌｌ領域６を形成するために全面にＣＶＤ（
化学反応気相析出）法による８ｉＱ１膜９を形成してこ
れをホトレジスジ処理で前記Ｐｍ領域の真中部分を窓開
し、ここからＰ（リン）等の不純輪番基板中に導入する
。 ｔｇ）このようにＮ聾チャネル部、Ｐ”ｌｉソース
部５、チャネル部となるＮ領域４上へ形成したＮ”ｌｌ
領域６を設けた後、ＰＳＧ（リン・シリケート・ガラス
）９ニヨり全面をパッジベージ冒ンし、電極取出し用ホ
トレジスト処理後、第２ＷＪに示すようにＡＪ又は１％
８ｉを含むＡＪの蒸着により電極１１を取出す。すなわ
ち、ポリ８ｉ層からゲート電極Ｇを取出し、前記ソース
部とＮ＋部を設けたチャネル部とを同一面上にてソース
電極Ｓを取出す。その後、基板１裏面からドレインとな
るべき電極りを’ｌ’１−Ｎｉ−Ａｇ等の蒸着により取
出す。前記Ｎ＋領領域形成にあたって基板に導入される
不純物はＰＱ（Ｊ、の気相デボジシ曹ンによるＰ（リン
）が用いられる。Thereafter, an N region 4 for forming a channel is selectively formed by ion implantation and shallow diffusion. (After the e1 period, the oxide film in the part that will become the source is etched by photoresist processing, and the Pg region is formed using the same mask used to form the channel part using the poly 8i mask. At this time, the Pm region is formed in the middle part of the source. without doing, ahead fjN
It is preferable to expose the ll formation region to the surface oxide film portion. (fl After that, CVD (
An 8iQ1 film 9 is formed by a chemical reaction vapor phase deposition method, and a window is opened in the center of the Pm region by photoresist processing, and an impurity such as P (phosphorus) is introduced into the rotational substrate from there. tg) In this way, N''ll formed on the N deaf channel section, the P''li source section 5, and the N region 4 that will become the channel section.
After forming the region 6, the entire surface of PSG (phosphorus silicate glass) 9 is padded, and after the photoresist treatment for electrode extraction, AJ or 1% is applied as shown in the second WJ.
Electrode 11 is taken out by vapor deposition of AJ containing 8i. That is, the gate electrode G is taken out from the poly 8i layer, and the source electrode S is taken out with the source part and the channel part provided with the N+ part on the same plane. Thereafter, an electrode layer to be a drain is taken out from the back surface of the substrate 1 by vapor deposition of 'l'1-Ni-Ag or the like. As the impurity introduced into the substrate in forming the N+ region, P (phosphorus) is used by vapor phase deposition of PQ (J).
前記のようにして製造された本発明によるＰチャネル形
のパワーＭＯ８ＦＥＴは第２図、第３図に示されるよう
に、従来型のｔ＆形ＰチャネルＭＯ８ＦＥＴに対して、
ソースとなるＰ＋領域５に隣接してチャネルとなるＮｉ
ｌ［領域４につながるようにＮｕｌｌ領域６を形成する
ものである。このようなＮＩｊＩＩ領域４上にＮ＋、型
領域６を設けない従来撤’） １ 子”ｉｃ’ Ｇｌ
、 ドレイン出力特性においてドレイン電流・電圧特
性が好ましくなかった。そしてＮｉｌチャネル部とソー
スのＡＪ電極との間にバリア（障壁）が形成され、その
結果チャネル部の電位が安定しないため通常はドレイン
電圧に対しドレイン電流が影響されない飽和領域におい
て出力特性がドレイン電圧に対し一定とならないし、又
リーク電流の増大といった問題が発生した。しかし、本
発明によればＮ微チャネ〃領域４につながるＮ＋型領領
域６形成することでドレイン出方特性において良好な動
作が得られる。すなわち、Ｎｌｌチャネル領域とＡＪＩ
ｌｉとがオーミックコンタクトされることでチャネルが
形成され、Ｎ截領域の電位が安定に決まり、従って安定
したＰＥＴ動作が可能となる。又、Ｎ＋＋チャネル領域
の抵抗が下げられるためブレークダウン時のＮ［領域の
電位の上昇がおさえられ破壊に対して強くなる。又、ソ
ース・ドレイン逆方向のＮＰＰ＋ダイオードのｖＦが低
く逆方向動作が可能である等の諸効果がもたらされる。As shown in FIGS. 2 and 3, the P-channel type power MO8FET according to the present invention manufactured as described above has the following characteristics compared to the conventional t& type P-channel MO8FET.
Ni which becomes the channel adjacent to the P+ region 5 which becomes the source
l[Null region 6 is formed so as to be connected to region 4. Conventionally, the N+ type region 6 is not provided on the NIjII region 4.
In terms of drain output characteristics, the drain current and voltage characteristics were unfavorable. A barrier is formed between the Nil channel part and the AJ electrode of the source, and as a result, the potential of the channel part is not stabilized. Normally, the output characteristics change depending on the drain voltage in the saturation region where the drain current is not affected by the drain voltage. However, problems such as an increase in leakage current occurred. However, according to the present invention, by forming the N+ type region 6 connected to the N fine channel region 4, good operation can be obtained in terms of drain characteristics. That is, the Nll channel region and the AJI
A channel is formed by making ohmic contact with li, and the potential of the N-cut region is stably determined, thus enabling stable PET operation. Furthermore, since the resistance of the N++ channel region is lowered, the increase in the potential of the N[ region at the time of breakdown is suppressed, making it resistant to breakdown. In addition, various effects such as low vF of the NPP+ diode with the source and drain in the reverse direction and the ability to operate in the reverse direction are brought about.
本発明の実施例ではＰチャネル形パワーＭＯ８ＦＢＴｋ
ｍついて説明したが、Ｎチャネル形パワーＭＯ８ＦＥＴ
についても同様に適用されるものである。In the embodiment of the present invention, P-channel type power MO8FBTk
Although I explained about m, N-channel type power MO8FET
The same applies to.
第１図（組〜Ｉｇ＋は本発明による縦形ＭＱ８ＦＥＴの
製造プロセスを示す工程断面図、第２図は本発明による
Ｐチャネル縦形ＭＯ８ＦＥＴの完成時の断面図、第３図
は第２図の要部拡大断面図である。
１・・・Ｐ” Ｍ８ ｔ＆＆、２・・・Ｐ型エピタキシ
ャル層、３・・・Ｎ型ウェル拡散層、４・・・Ｎ豫チャ
ネル部拡散層、５・・・Ｐ＋型ソース領域、６・・・チ
ャネル部コンタクトＮ＋領域、７・・・ゲート酸化膜、
８・・・ポリＳｔゲート電極、９・・・Ｐ２Ｏ膜、１ｏ
・・・フィールド酸化膜、１１・・・ＡＪＩ （８ｉ入
り）電極、１２・・・裏面電極（ドレイン）。
第 １ 図
（６−）
第 １ 図
第−２図Figure 1 (Group ~ Ig+ is a process cross-sectional view showing the manufacturing process of the vertical MQ8FET according to the present invention, Figure 2 is a cross-sectional view of the completed P-channel vertical MO8FET according to the present invention, and Figure 3 is the main part of Figure 2. It is an enlarged cross-sectional view. 1... P" M8 t&&, 2... P type epitaxial layer, 3... N type well diffusion layer, 4... Nyo channel part diffusion layer, 5... P+ type source region, 6... channel part contact N+ region, 7... gate oxide film,
8... PolySt gate electrode, 9... P2O film, 1o
. . . Field oxide film, 11 . . . AJI (8i included) electrode, 12 . . . Back electrode (drain). Figure 1 (6-) Figure 1 Figure-2
Claims (1)
一部にチャネル部のつくられる第２導電型領域を形成し
、チャネル部となる第２導電型領域表面に絶縁膜を介し
てゲートを設け、チャネル部とならない第２導電型領域
表面にソースとなる第１導電１１［［域を′形成し、こ
の第１導電型領域に近接して第２導電型高濃度領域を形
成するとともに上記第１導電型領域上及び第２・・導電
型高濃度領域上にこれらを短絡するソース電極を！！赦
して成、るこ□とを特徴とするＩ１１１００８ＦＥＴ。1. A second conductivity type region where a channel portion is formed is formed on a part of the main surface of the first conductivity type semiconductor substrate that will become the drain, and a gate is formed on the surface of the second conductivity type region that will become the channel portion via an insulating film. A first conductive region 11[[['] which becomes a source is formed on the surface of the second conductive type region that does not become a channel portion, and a second conductive type high concentration region is formed in proximity to this first conductive type region. A source electrode is placed on the first conductivity type region and the second conductivity type high concentration region to short-circuit them! ! I111008FET is characterized by forgiving and forming, Ruko□.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113713A JPS5816569A (en) | 1981-07-22 | 1981-07-22 | Vertical type mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113713A JPS5816569A (en) | 1981-07-22 | 1981-07-22 | Vertical type mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5816569A true JPS5816569A (en) | 1983-01-31 |
Family
ID=14619260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56113713A Pending JPS5816569A (en) | 1981-07-22 | 1981-07-22 | Vertical type mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5816569A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59122362U (en) * | 1983-02-07 | 1984-08-17 | スガツネ工業株式会社 | hinge |
| US4680604A (en) * | 1984-03-19 | 1987-07-14 | Kabushiki Kaisha Toshiba | Conductivity modulated MOS transistor device |
| US4686551A (en) * | 1982-11-27 | 1987-08-11 | Nissan Motor Co., Ltd. | MOS transistor |
| US4803532A (en) * | 1982-11-27 | 1989-02-07 | Nissan Motor Co., Ltd. | Vertical MOSFET having a proof structure against puncture due to breakdown |
-
1981
- 1981-07-22 JP JP56113713A patent/JPS5816569A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4686551A (en) * | 1982-11-27 | 1987-08-11 | Nissan Motor Co., Ltd. | MOS transistor |
| US4803532A (en) * | 1982-11-27 | 1989-02-07 | Nissan Motor Co., Ltd. | Vertical MOSFET having a proof structure against puncture due to breakdown |
| JPS59122362U (en) * | 1983-02-07 | 1984-08-17 | スガツネ工業株式会社 | hinge |
| US4680604A (en) * | 1984-03-19 | 1987-07-14 | Kabushiki Kaisha Toshiba | Conductivity modulated MOS transistor device |
| USRE32784E (en) * | 1984-03-19 | 1988-11-15 | Kabushiki Kaisha Toshiba | Conductivity modulated MOS transistor device |
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