JPS6041264A - Transistor - Google Patents
TransistorInfo
- Publication number
- JPS6041264A JPS6041264A JP14943984A JP14943984A JPS6041264A JP S6041264 A JPS6041264 A JP S6041264A JP 14943984 A JP14943984 A JP 14943984A JP 14943984 A JP14943984 A JP 14943984A JP S6041264 A JPS6041264 A JP S6041264A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- semi
- semiconductor layer
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 229910052721 tungsten Inorganic materials 0.000 abstract description 9
- 239000010937 tungsten Substances 0.000 abstract description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 244000126211 Hericium coralloides Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はＰｅｒｍｅａｂｌｅＢａｓｅ ＴｒａｎｓｊＳ
ｔ、ｏｒ （以下、ＰＢＴ素子と称する）に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to PermeableBase TransjS
t, or (hereinafter referred to as a PBT element).
ＰＢＴ素子は半導体基体中に櫛の歯状に挿入された金属
ベースと、この金属ベースをはさんで、前記半導体基体
の上下面にエミッタとコレクタ電極を設けた構造を有す
る素子である。この素子に関してはＣ，Ｏ，Ｂｏｚｌ、
ｅｒ ｅｔ ａｌ、、“Ｐ ｅｒｍＯａｂｌ、ｅＢａｓ
ｅ Ｔｒａｎｓｉｓｔｏｒ″ Ｐｒｏｃ、７ｔｈ ｎｊ
ｃｎｎｊａｌＣｏｒｎｅ］ｌ Ｅｌｅｃｔｒｉｃａｌ
ＥｎｇｉｎｅｅｒｊｎｇＣｏｎｆｅｒｅｎｃｅ ｏｎ
Ａｃｔｉｖｅ ＭｊｃｒｏｗａｖｃＳｅｍｉｃｏｎｄｕ
ｃｔｏｒ Ｄｅｒｊ、ｃｅｓ、 Ａｕｇ、 １９７０に
詳しい。この構造と動作を略述すると次の通りである。A PBT element is an element having a structure in which a metal base is inserted into a semiconductor substrate in the shape of a comb, and emitter and collector electrodes are provided on the upper and lower surfaces of the semiconductor substrate with the metal base sandwiched therebetween. Regarding this element, C, O, Bozl,
er et al., “P ermOabl,eBas
e Transistor'' Proc, 7th nj
cnnjalCorne]l Electrical
Engineer Conference on
Active MjcrowavcSemicondu
Director Derj, ces, Aug, 1970. The structure and operation are briefly described below.
ｎ＋型半導体基板、ｎ型エミッタ層、タングステン・グ
レーティ９ング層、およびｎ型コレクタ層の４層が積層
されている。このタングステン・グレーティングは、た
とえば３２００人周期、１６００人の櫛の歯の幅という
ように非常に狭いので、この間は空乏層となる。上記エ
ミツタ層はその両側を、たとえばプロトン打込み領域等
によって囲われ、ｎ＋半導体基板からエミツタ層へのエ
レクトロンの流れは所定部分に制限されている。Four layers are stacked: an n+ type semiconductor substrate, an n type emitter layer, a tungsten grating layer, and an n type collector layer. This tungsten grating is very narrow, for example, with a period of 3,200 people and a width of 1,600 comb teeth, so the period becomes a depletion layer. The emitter layer is surrounded on both sides by, for example, a proton implantation region, and the flow of electrons from the n+ semiconductor substrate to the emitter layer is restricted to a predetermined portion.
従って、エミツタ層からコレクタ層へは上記タングステ
ン・グレーテイング層を通して、エレクトロンが流れる
ようになっている。Therefore, electrons flow from the emitter layer to the collector layer through the tungsten grating layer.
上記ベースの電圧を変化させることにより、工ミッタか
らタングステン・グレーティングの櫛の歯の間を通って
コレクタへ流れるキャリアの量を制限する。Varying the voltage at the base limits the amount of carrier flowing from the emitter through the comb teeth of the tungsten grating to the collector.
本発明はこのＰＢＴ素子の改良で、特に集積化に適した
ものである。The present invention is an improvement of this PBT element, and is particularly suitable for integration.
本発明の要点は、半絶縁性基板を用い、エミッタとコレ
クタを同一方向に導出し、集積化に好都合な構成とした
ことにある。更に半絶縁性基板を用いることにより、浮
遊容量の低減をはかることが出来、従ってＰＢＴの高速
性が生かされる。The key point of the present invention is that a semi-insulating substrate is used, the emitter and the collector are led out in the same direction, and the configuration is convenient for integration. Furthermore, by using a semi-insulating substrate, stray capacitance can be reduced, and therefore the high speed performance of PBT can be utilized.
以下、実施例を基に本発明を説明する。 The present invention will be explained below based on Examples.
第１図（ａ）〜（ｆ）にＰＢＴ素子の製造工程の各段階
を示す、素子断面図である。FIGS. 1(a) to 1(f) are device cross-sectional views showing each stage of the manufacturing process of the PBT device.
Ｇ ａ Ａ ｓ半絶縁性基板１シ二フォトレジストをマ
スクとして、Ｓイオンをドーズ量１０ ” ｃｍ−”で
イオン打込みし、その後水素中で８５０℃、３０分間熱
処理してｎ＋層２を形成する（第１図（ａ））。GaAs semi-insulating substrate 1 Using the photoresist as a mask, S ions are implanted at a dose of 10 cm-, and then heat treated in hydrogen at 850°C for 30 minutes to form an n+ layer 2. (Figure 1(a)).
ＡｓＣＱ ３− Ｇａ −）（２系の気相成長法により
、２ＸＩＯ”ｃｍ３のキャリア濃度のｎ形ＧａＡｓエピ
タキシャル層３′を１．５μｍ成長させる。気相成長法
そのものは周知の方法に従えば良い。このエピタキシャ
ル層上にタングステン膜４′を厚さ２００人蒸着する（
第１図（ｂ）） 。その後、ＡＺ−１３５０（シップレ
イ社製品番号）フォトレジストを塗布し、４５８０人の
Ａｒレーザの干渉パターンで露光する。次いでＪＵ＆＜
＋処理によって格子パターンを形成する。これをマスク
としてタングステンを櫛の歯状４にエッチする（第１図
（Ｃ））。An n-type GaAs epitaxial layer 3' having a carrier concentration of 2XIO"cm3 is grown to a thickness of 1.5 μm by AsCQ 3-Ga-) (2-based vapor phase growth method. The vapor phase growth method itself can be performed according to a well-known method. A tungsten film 4' is deposited on this epitaxial layer to a thickness of 200 mm (
Figure 1(b)). Thereafter, AZ-1350 (Shipley product number) photoresist is applied and exposed with a 4580 Ar laser interference pattern. Then JU&<
A lattice pattern is formed by the + process. Using this as a mask, tungsten is etched into a comb tooth pattern 4 (FIG. 1(C)).
この櫛の歯の周期は３０００人であり、櫛の歯の間隙は
１５００人である。この様にして、櫛の歯状のタングス
テン膜４が形成される。このウェーハ上に前述した気相
成長法により、ｎ形ＧａＡｓ層（キャリア濃度： ２
Ｘ Ｉ Ｑ”ｃｍＶ３）を０．５ μｍ成長させる。間
隙の部分でまずエピタキシャル成長がおこり、その後横
方向に広がるため、全面にＧ ａ Ａ ｓ層３＃がエピ
タキシャル成長する（第１図（ｄ））。ｎ＋層２からの
電極を取り出すために、３−
Ｓイオンを部分的に打込みｎ＋層５を形成する。The period of the teeth of this comb is 3000 people, and the gap between the teeth of the comb is 1500 people. In this way, a comb-like tungsten film 4 is formed. An n-type GaAs layer (carrier concentration: 2
X I Q"cmV3) is grown to a thickness of 0.5 μm. Epitaxial growth occurs first in the gap, and then spreads laterally, so that a Ga As layer 3# is epitaxially grown over the entire surface (Fig. 1 (d)). In order to take out the electrode from the n+ layer 2, 3-S ions are partially implanted to form the n+ layer 5.
その後、素子間の絶縁のためにＨ＋を打込み半絶縁領域
６を形成する（第１図（ｅ））−ＡｕＧｅＮｉ合金を蒸
着して、フォトレジ工程を用い、エミッタ電極７および
コレクタ電極８を形成する（第１図（ｆ））。After that, H+ is implanted to insulate between elements to form a semi-insulating region 6 (FIG. 1(e)) - AuGeNi alloy is deposited, and an emitter electrode 7 and a collector electrode 8 are formed using a photoresist process. (Figure 1(f)).
第２図はＰＢＴ素子の斜視図である。第１図と同一番号
の部分は同一部位である。なお、３は３′および３”を
合わせたＧ ａ Ａ ｓ層として示しである。FIG. 2 is a perspective view of the PBT element. Portions with the same numbers as in FIG. 1 are the same parts. Note that 3 is shown as a Ga As layer including 3' and 3''.
この様にして製作したＰＢＴ集積回路素子は半絶縁性基
板上に形成されているので、寄生容量が少ない。また、
ＰＢＴの特徴であるベース巾が小さいこと、ベース抵抗
が小さいことからくる高速性と合わせると、高速の論理
用集積回路ができる。Since the PBT integrated circuit element manufactured in this manner is formed on a semi-insulating substrate, it has little parasitic capacitance. Also,
When combined with the small base width and high speed resulting from low base resistance, which are characteristics of PBT, it is possible to create a high-speed logic integrated circuit.
１００ゲートの論理用集積回路で１ゲート当りの遅延時
間５０ｐｓが得られた。A delay time of 50 ps per gate was obtained in a logic integrated circuit with 100 gates.
第１図（ａ）〜（ｆ）はＰＢＴ素子の製造工程を示す素
子断面図、第２図はＰＢＴ素子の斜視図である。
４−
■・・・半絶縁性の半導体基板、２・・・不純物領域、
３・・・Ｇ ａ Ａ ｓ層、４・・・タングステン・グ
レーティング、５・・・不純物領域、６・・・絶縁領域
、７，８・・・金属電極・
な１図
矛 １ 図FIGS. 1(a) to 1(f) are cross-sectional views of the PBT element showing the manufacturing process of the PBT element, and FIG. 2 is a perspective view of the PBT element. 4- ■... Semi-insulating semiconductor substrate, 2... Impurity region,
3...G a As layer, 4... Tungsten grating, 5... Impurity region, 6... Insulating region, 7, 8... Metal electrode.
Claims (1)
る半導体層と、この電流通路を構成する半導体層中に配
され電流を制御する金属格子とを有し、前記電流通路を
構成する半導体層の上面には第１の電極、前記電流通路
を構成する半導体層の下面は前記半絶縁性半導体基板中
に設けられた不純物領域を通して前記半導体層」二面の
第２の電極に電気的に接続されて成ることを特徴とする
１〜ランジスタ。A semiconductor comprising a semiconductor layer forming a current path provided in a semi-insulating semiconductor substrate, and a metal lattice disposed in the semiconductor layer forming the current path and controlling the current, and forming the current path. A first electrode is provided on the upper surface of the layer, and a second electrode on the second surface of the semiconductor layer is electrically connected to the lower surface of the semiconductor layer constituting the current path through an impurity region provided in the semi-insulating semiconductor substrate. 1. A transistor characterized by being connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14943984A JPS6041264A (en) | 1984-07-20 | 1984-07-20 | Transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14943984A JPS6041264A (en) | 1984-07-20 | 1984-07-20 | Transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6041264A true JPS6041264A (en) | 1985-03-04 |
Family
ID=15475137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14943984A Pending JPS6041264A (en) | 1984-07-20 | 1984-07-20 | Transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6041264A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212404A (en) * | 1990-04-09 | 1993-05-18 | Fujitsu Limited | Semiconductor device having a vertical channel of carriers |
-
1984
- 1984-07-20 JP JP14943984A patent/JPS6041264A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212404A (en) * | 1990-04-09 | 1993-05-18 | Fujitsu Limited | Semiconductor device having a vertical channel of carriers |
| US5296390A (en) * | 1990-04-09 | 1994-03-22 | Fujitsu Limited | Method for fabricating a semiconductor device having a vertical channel of carriers |
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