JPS63318778A - Heterojunction bipolar transistor and manufacture - Google Patents

Abstract

PURPOSE:To obtain a heterojunction bipolar transistor which is more improved in high speed and high frequency performance thereof, by providing on the surface of a semi-insulating substrate with a portion of an external area for connection of a base layer, and so forth to reduce a base-collector parasitic capacity without increasing a base resistance. CONSTITUTION:A collector layer 2 of one conductivity type which is selectively formed on the surface of a semi-insulating substrate 1, a base layer 3 of the opposite conductivity type whose an active area and a portion of an extension area for connection are respectively formed on the collector layer 2 and the semi-insulating substrate 1, and an emitter layer 4 of one conductivity type which is formed on the active area of the base layer 3 are provided, respectively. For example, a collector layer 2 of a n type GaAs is selectively formed on the surface of a semi-insulating substrate 1 of a GaAs, a base layer 3 of a p type GaAs is formed on both of a portion of the active area of the collector layer 2 and the semi-insulating substrate 2, and an emitter layer 4 of an n-type AlGaAs is formed just above the active area of the collector layer 2. Moreover, electrodes 5c, 5b and 5e are formed on the respective predetermined portions of the layers 2, 3 and 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a heterojunction bipolar transistor and a method for manufacturing the same.

[Conventional technology]

In recent years, active research and development has been carried out to increase the integration and speed of semiconductor devices. In particular, we focus on heterojunction bipolar transistors that utilize heterojunctions such as compound semiconductors (
HBT (hereinafter referred to as HBT) has recently attracted attention as a device with high gain and high speed performance because it can maintain high emitter injection efficiency even when the base concentration is high. This has become possible due to advances in compound semiconductor thin film multilayer process technology, such as ion implantation technology and ion implantation technology.

By the way, one index representing the high-speed/high-frequency characteristics of the pibora transition is the maximum oscillation frequency fmax, which is expressed by the following equation.

Here, fi is the current gain cutoff frequency, RIB is the pace resistance, CBc is the pace-collector junction capacitance in the active region, and C
bc is the pace collector parasitic junction capacitance in the external pace region.

Therefore, as is clear from equation (1), in order to increase the maximum oscillation frequency f□8 and improve the high- and high-frequency performance of the HBT, the pace resistor kLB and the pace cov l fi
! It is necessary to make the m-total capacitance C100%, especially the pace-collector parasitic junction capacitance Cbc, as small as possible.

Therefore, conventionally, oxygen ions, hydrogen ions, etc. are selectively implanted with high energy through the external base region.
By forming a semi-insulating layer at the pace-collector junction, the pace-collector parasitic junction capacitance Cbck was reduced.

FIG. 4 is a sectional view of an example of a conventional IBT.

In this example, a collector layer 2' made of nmGaAs, a base layer 3' made of p-type (JaAs), and an emitter layer 4 made of n-type klGaAs are sequentially formed on a semi-insulating substrate l, and the base layer A semi-insulating layer 1a is formed by selectively implanting oxygen ions or hydrogen ions into the interface between the external space region for connection other than the active region immediately below the emitter layer 4 of 3I and the collector layer l below it. By this, the paste-collector parasitic junction capacitance Cbc is reduced, and the collector, paste and emitter layers 2
Collector, pace and emitter electrodes 5C, 5b and 5 above respective predetermined positions of /, 3/ and 4
ei has been established.

[Problem that the invention seeks to solve]

In the conventional HBT described above, the base layer and the collector layer face each other via the semi-insulating layer formed by ion implantation in the external space region, so that the external space/collector parasitic capacitance f! kCbc can be reduced by about 30 to 40 at most. In addition, crystal defects are generated in the external space region directly under the space electrode 5b due to the implantation when forming the semi-insulating layer, but some of these defects remain even after heat treatment, and these defects act as carrier traps. , the pace resistance RB increases significantly.

As a result, as shown in equation (1), in the conventional HBT, C
Even if bc is slightly reduced, RB increases significantly, so the maximum oscillation frequency fm□ tends to decrease, making it difficult to dramatically improve high-speed/high-frequency performance.

An object of the present invention is to provide a beta-junction bipolar transistor with further improved high-speed and high-frequency performance in which the pace-collector parasitic capacitance CbC is reduced without increasing the pace resistance, and a method for manufacturing the same.

[Means for solving problems]

The heterojunction bipolar transistor of the present invention has a collector layer selectively formed on the surface of a semi-insulating substrate, and an active region and a connection drawer formed on the collector layer and the semi-insulating substrate, respectively. The active region has a base layer of opposite conductivity type forming a portion of the active region, and an emitter layer of one conductivity type formed close to the active region of the base layer.

The method for manufacturing a heterojunction bipolar transistor of the present invention includes a step of selectively forming a collector layer of one conductivity type on the surface of a semi-insulating substrate, a step of selectively forming a collector layer of one conductivity type on the surface of a semi-insulating substrate, and a step of forming a first collector layer of an opposite conductivity type on a core collector layer and the semi-insulating substrate. the step of sequentially depositing an impurity layer and a second impurity layer of a conductive type, and selectively and sequentially removing the second and first impurity layers, respectively, on the collector layer and the semi-insulating substrate; A base layer made of the first impurity layer and an emitter layer made of the second impurity layer placed on the active region are formed on the active region and the connection lead-out region, respectively.

[Function] According to the present invention, since the external base region portion of the base layer is provided on the surface of the semi-insulating substrate, the opposing area between the base layer and the collector layer is reduced, thereby preventing pace collector parasitics. Junction capacitance can be made extremely small.

〔Example〕

Next, a nail embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention.

In this embodiment, a semi-insulating substrate 1 made of GaAs is used.
A collector layer 2 with a predetermined pattern made of n-uaAs is selectively provided on the surface, a base layer 3 made of p-GaAs is provided on the active region portion of the collector layer 2 and on the semi-insulating substrate 1, and the collector layer 2 is provided with a predetermined pattern. n-AI (j
An emitter layer 4 made of aAs is provided, and collector, base and emitter electrodes 5c and 5b are provided at predetermined portions on the collector, base and emitter layers 2.3 and 4, respectively.
and 5e.

Therefore, in this embodiment, the base electrode 5b of the base layer 3
Since the collector layer 2 is not directly under the external base region for connection and is provided directly on the semi-insulating substrate 1, the facing area between the base layer 3 and the collector layer 2 becomes very small. .

FIGS. 2(a) to 2(C) are cross-sectional views of a semiconductor chip for explaining the first embodiment of the HBT manufacturing method of the present invention.

In this embodiment, first, as shown in FIG. 2(a),
A mask layer 6 of a predetermined pattern made of an insulating film such as KSi02 or 8i3N4 is formed on a semi-insulating substrate 1 made of aAs, and then this mask layer 6 is used to cover the surface of the semi-insulating substrate 1 with a thickness of about 0.5 μm. Etch to depth.

Next, as shown in Figure 2(b), the atomic
By ear epitaxy (mono-atomic layer growth) method, a thickness of 0.5μ of n-GaAs is formed in the recessed part of the semi-insulating substrate 1.
A monoatomic layer 2a of about m thickness is formed and embedded.

Next, as shown in FIG. 2(C), the i-sk I @ 6 k
After removal, an impurity layer 3a made of p-GaAs and having a thickness of about 0.1 μm and an impurity layer 4at made of n-AlGaAs and having a thickness of about 0.2 μm are sequentially formed by epitaxial growth.

Finally, impurity layers 4a and 3at are formed by a well-known method.
- After etching into a predetermined pattern to form an emitter layer 4 and a base layer 3, respectively, the monoatomic layer 2a is used as a collector layer 2, and an emitter electrode 5e and a collector electrode 5C made of ohmic contact metal Auue/Ni for nGaAs are formed. If a base electrode 5bt made of ohmic contact metal AuZn/Ni is formed on p-GaAs, the HBT shown in FIG. 1 can be obtained. 3(a) to 3(C) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the method for manufacturing an IBT according to the present invention.

In this example, first, as shown in FIG. 3(a), Ga
5iOz or Si on a semi-insulating substrate 1 made of As.
A mask layer 6 of a predetermined pattern made of an insulator such as 3N4 is formed.

Next, as shown in FIG. 3(b), using this mask layer 6, Si ions are implanted into the exposed surface of the semi-insulating substrate 1, and further activated by heat treatment to form an ion implanted layer 2b.

Next, as shown in FIG. 3(C), a p-U film with a thickness of about 0.1 μm is placed on the second half insulating substrate l from which the mask layer 6 has been removed.
An impurity layer 3a made of aAs and an impurity layer 4a made of n-AlGaAs having a thickness of about 0.2 μm are sequentially formed by epitaxial growth.

Finally, the impurity layers 4a and 3a are sequentially etched in a predetermined pattern to form an emitter layer 4 and a base layer 3, respectively, and 1pln is etched on predetermined portions of the collector layer 2 and emitter layer 4 consisting of the ion implantation layer 2b. −
Ohmic contact metal A u'J e for GaAs
By forming a collector electrode 5C and an emitter electrode set made of /Nt, and further forming a pace electrode 5b made of ohmic contact metal AuZn/Ni at a predetermined position on the base layer 3, an IBT (as shown in FIG. 1) is obtained. Can be done.

〔Effect of the invention〕

As explained above, according to the present invention, since the external region for connection of the base layer is provided on the surface of the semi-insulating substrate, the facing area between the base layer and the collector layer is greatly reduced. Since the base-collector parasitic junction capacitance Cbc is reduced and the increase in the pace resistance iLB caused by conventional ion implantation for forming a semi-insulating layer can be prevented,
This has the effect of realizing a taheterojunction bipolar transistor with an extremely high maximum oscillation frequency f□8 and excellent high-speed and high-frequency performance.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an embodiment of the heterojunction biborder transistor of the present invention, and FIGS. 2 and 3 (a) to (C)
4 is a cross-sectional view of a semiconductor chip for explaining the first and second embodiments of the method for manufacturing a heterojunction bipolar transistor of the present invention, respectively, and FIG. 4 is a cross-sectional view of an example of a conventional heterojunction bipolar transistor. be. 1...Semi-insulating substrate, la...Semi-insulating layer, 2゜2I...Collector layer%2a...
- Monoatomic layer, 2b...Ion implantation layer, 3.3'
...Pace layer, 3a... Impurity layer, 4
...Emitter layer, 4a... Impurity layer,
Volume 4 Figure 2 (α) 1 (b)l 3rd concave

Claims (2)

[Claims] (1) A collector layer of one conductivity type selectively formed on the surface of a semi-insulating substrate, and an opposite conductivity type having an active region and a connection lead-out region formed on the collector layer and the semi-insulating substrate, respectively. and an emitter layer of one conductivity type formed over the active region of the base layer. (2) A step of selectively forming a collector layer of one conductivity type on the surface of a semi-insulating substrate, and a first impurity layer of an opposite conductivity type and a second impurity layer of one conductivity type are formed on the collector layer and the semi-insulating substrate. and selectively and sequentially removing the second and first impurity layers, respectively, forming an active region and a connection lead-out region on the collector layer and the semi-insulating substrate, respectively. A method for manufacturing a heterojunction bipolar transistor, comprising forming a base layer made of the first impurity layer disposed on the active region and an emitter layer made of the second impurity layer disposed on the active region.