JPH01233767A - Heterojunction bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To make B-E and B-C junction areas minute by a method wherein a position and a size of an intrinsic base layer or the intrinsic base layer and a collector layer in a transistor are prescribed individually by a wall edge of a taperlike insulating layer formed on a mesa sidewall of an emitter layer. CONSTITUTION:A collector layer 12 is formed on a semiinsulating semiconductor substrate 11; a thick external base layer 17 is laminated on the collector layer; a taperlike insulating layer 15 whose film thickness is increased gradually toward the base layer is provided on mesa sidewalls. In addition, a mesa-shaped emitter layer 14 is formed in such a way that it is filled into the thick external base layer 17; an intrinsic base layer 13 is formed inside the external base layer 17 surrounded by the taperlike insulating layer 15. By this setup, a base- emitter junction capacitance in the intrinsic base region can be reduced without increasing an emitter resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a heterojunction bipolar transistor and a method of manufacturing the same.

[Conventional technology]

In recent years, vigorous research and development has been carried out on semiconductor devices to achieve higher integration and higher speed. In particular, bipolar transistors (hereinafter referred to as H
BT) is expected to have high emitter injection efficiency, high gain, and high speed, and is attracting attention as a next-generation semiconductor device. This HBT has become possible with the advancement of thin film multilayer crystal growth technology for compound semiconductors using molecular beam epitaxial growth, organometallic pyrolysis vapor phase epitaxy, and the like.

In this HBT, one index representing the high speed/high frequency characteristics is the maximum oscillation frequency f max, which is generally expressed by the following equation.

ftbeg m/Cng...(
2) Here, fT is the current gain cutoff frequency, RB is the base resistance, CBC is the base-collector junction capacitance in the transistor's true region, Cbc is the base-collector parasitic capacitance in the external base region of the transistor + CBE is the transistor's veracity The base-emitter capacitance of the region +gsa is the transconductance of the transistor.

As is clear from the above equation, one way to realize an HBT that operates at high speed is to maintain a large value of the transconductance g of the transistor while increasing the base resistance RB, base-emitter capacitance CBE, and base-emitter capacitance in the veracity region. The purpose is to set each of the collector junction capacitance CBc and the base-collector parasitic capacitance Cbo of the external base region as small as possible. Therefore, the development of HBTs has conventionally been carried out in accordance with this development method, and has been strongly promoted with emphasis on miniaturization of the true region of transistors.

Figure 6 shows the conventional npn type A j' G a A s /
1 is a chip cross-sectional view showing the structure of a GaAs heterojunction bipolar transistor. FIG. That is, conventional HBT
A collector layer 2 made of n-type GaAs, a base layer 3 made of p-type GaAs, and n
Type A! ! A mesa-shaped emitter layer 4 made of GaAs is provided, and an emitter electric current f! is provided on the surface of each transistor active layer. A 6° base electrode 8 and a collector electrode 9 are each formed into a fine structure.

[The problem that the invention attempts to solve]

In such a conventional HBT structure, the base-emitter junction capacitance CBE in the true region can be reduced by minimizing the junction area between the emitter layer 4 and the base layer 3. However, if the emitter layer 4 is processed by dry etching or wet etching to make the base-emitter junction area finer, the contact area between the emitter layer 4 and the emitter electrode 3 will also become smaller. Although the emitter junction capacitance CBE is reduced, on the other hand the contact resistance between the emitter layer 4 and the emitter electrode 6 increases. That is, the emitter resistance increases and the transconductance g of the transistor decreases. Therefore, since the effect of reducing the base-emitter junction capacitance CBI is offset by the reduction in mutual conductance g11, it is difficult to improve the current gain cutoff frequency f↑ and the maximum oscillation frequency f max. Also, this HB
In the structure of T, when the depth of the true base layer is determined, the thickness of the base layer 3 is also uniquely determined, and the size of the base resistance RB is also determined, so it is difficult to reduce the base resistance Ra. Base-collector junction capacitance CSC in the veracity region
and the base-collector parasitic capacitance Cb of the external base region
Since it is extremely difficult to reduce c due to the valve structure,
With the conventional HBT structure, better high speed and high frequency characteristics cannot be obtained.

In view of the above circumstances, an object of the present invention is to reduce the base-emitter junction capacitance of the true base region without increasing the emitter resistance, and to reduce the base resistance and the base-collector junction of the true region. It is an object of the present invention to provide a heterojunction bipolar transistor having a structure capable of reducing both capacitance and base-collector parasitic capacitance in an external base region, and a method for manufacturing the same.

[Means to solve the problem]

According to the present invention, one of the heterojunction bipolar transistors includes a semi-insulating semiconductor substrate, a collector layer formed on the substrate, a thick external base layer laminated on the collector layer, a mesa-shaped emitter layer provided with a tapered insulating layer whose film thickness increases sequentially toward the base layer on a mesa side wall and formed to be embedded in the thick external base layer; and the mesa-shaped emitter layer. a solid base layer formed in the plane of the external base layer surrounded by the edge of the tapered insulating layer, and an emitter electrode and a base electrode provided on the upper surfaces of the mesa-shaped emitter layer, the external base layer, and the collector layer, respectively. and a collector electrode, and the other one includes a semi-insulating semiconductor substrate, an external collector layer formed on the substrate, and a semi-insulating semiconductor substrate formed sequentially on the external collector layer. A spacer layer made of a semiconductor material and a thick outer base layer; and a tapered insulating layer on a mesa sidewall that gradually increases in thickness toward the base layer, and is embedded in the thick outer base layer. a mesa-shaped emitter layer formed in the mesa-shaped emitter layer, and a true base layer and a true collector layer respectively formed in the plane of the outer base layer and the spacer layer surrounded by the edge of the tapered insulating layer of the mesa-shaped emitter layer. , an emitter electrode provided on the upper surface of the mesa-shaped emitter layer, the external base layer, and the external collector layer, respectively.

It is configured to include a base electrode and a collector electrode.

Further, one of the manufacturing methods of the present invention includes a step of sequentially epitaxially growing a collector layer and a thick-film external base on a semi-insulating semiconductor substrate, and forming a groove portion of a predetermined depth on the thick-film external base layer. and a step of selectively forming a tapered insulating layer whose thickness increases sequentially toward the base layer on the sidewall surface of the groove of the external base layer.

selectively etching the external base layer using the pattern of the tapered insulating layer as a mask to remove the external base layer at the bottom of the groove until the lower collector layer is exposed; and etching the exposed surface of the collector layer in the groove. a selective epitaxial growth step of forming a base layer; a step of forming a mesa-shaped emitter layer on the solid base layer by selectively epitaxially growing an emitter layer along the sidewall surface of the tapered insulating layer; The other step includes forming an emitter electrode, a base electrode, and a collector electrode on the upper surfaces of the emitter layer, the external base layer, and the collector layer, respectively.
a step of epitaxially growing a spacer layer made of a semi-insulating semiconductor material or an insulating material and a thick external base layer; a selective etching step of forming a groove of a predetermined depth on the external base layer; and a step of selectively etching the external base layer. A step of selectively forming a tapered insulating layer whose thickness increases sequentially toward the base layer on the side wall surface in the groove of the layer, and forming an external base layer and a spacer layer at the bottom of the groove by using the tapered insulating layer pattern as a mask. a selective etching step of the outer base layer and the spacer layer to remove the outer collector layer until the collector layer is exposed; and selective epitaxial growth to sequentially form a true collector layer and a true base layer on the exposed surface of the outer collector layer in the trench. forming a mesa-shaped emitter layer on the solid base layer, selectively epitaxially growing an emitter layer along the sidewall surface of the tapered insulating layer; the mesa-shaped emitter layer, the external base layer and and an extraction electrode forming step of forming an emitter electrode, a base electrode, and a collector electrode on the upper surface of the external collector layer, respectively.

At this time, a selective etching process of the external base layer is performed, using the pattern of the tapered insulating layer as a mask to remove the external base layer at the bottom of the groove until the spacer layer below is exposed, and an exposed surface of the spacer layer in the groove. a step of forming a true collector layer by ion implantation, in which impurities are ion-implanted using the pattern of the tapered insulating layer as a mask, and a selective epitaxial growth step of forming a true base layer on the true collector layer. But that's fine.

[Effect]

According to the present invention, the base-emitter junction area of the true region of the transistor, or both this and the base-collector junction area of the true region, is the base layer of the tapered insulating layer provided on the mesa wall of the emitter layer. The thickness of the neighborhood is defined accordingly. In other words, the junction area between these two is the mesa of the emitter layer.

Due to the presence of the tapered insulating layer provided on the wall, the contact area between the emitter layer and the emitter electrode is defined to be smaller than the contact area between the emitter layer and the emitter electrode. As a result, the base-emitter junction capacitance CBC in the true region remains set sufficiently wide without narrowing the contact area between the emitter layer and the emitter electrode, that is, it is reduced without increasing the emitter resistance.

With the true base layer and collector layer defined in this way, the thicknesses of the external base layer and the external collector layer can be freely set. That is, by making the external base layer sufficiently thick to greatly reduce the base resistance Ra, and by interposing a spacer layer between the external base layer and the external collector layer, the base-collector contact in the true region can be improved. The base area of the external and base area along with the gold capacitance CBc
Collector parasitic capacitance Cbc can be reduced at the same time.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

4 Fig. 1 shows an npn type AIG a showing an embodiment of the present invention.
As / Ga As heterojunction bipolar
FIG. 2 is a cross-sectional view of a transistor chip. According to this embodiment, the HBT of the present invention includes a semi-insulating semiconductor substrate 11 made of GaAs, and an n-type GaAs semiconductor substrate 11 formed on this substrate 11.
and a thick external base layer 17 made of n-type GaAs laminated on the collector layer 12.
A tapered insulating layer 15 whose film thickness gradually increases toward the base layer is provided on the side wall of the mesa, and an n-type Aj7Ga is formed so as to be embedded in the thick base layer 17.
A mesa-shaped emitter layer 14 made of As, a true base layer 13 made of n-type GaAs formed within the plane of the external base layer 17 surrounded by the edge of the tapered insulating layer 15, and a mesa-shaped emitter layer 14. External base layer 17 and collector layer 12
Emitter electrodes 16. It includes a base electrode 18 and a collector electrode 19.

According to this embodiment, the emitter layer 14 and the true base layer 13
The contact area between the emitter layer 14 and the emitter electrode 16 is reduced regardless of the size of the contact area established between the emitter layer 14 and the emitter electrode 16, and since the external base layer 17 is formed to have an arbitrary thickness, the emitter resistance can be reduced. The base-emitter junction capacitance CBE in the veracity region without increasing, i.e. decreasing g,
and the size of the base resistance RB can be reduced. Therefore, the upper limits of the maximum oscillation frequency f max and the current gain cutoff frequency ft are significantly extended, and the high speed/high frequency characteristics are significantly improved.

FIG. 2 shows another embodiment of the present invention.
1 is a chip cross-sectional view of an aAs/GaAs heterojunction bipolar transistor; FIG. According to this embodiment, the HBT of the present invention includes a semi-insulating semiconductor substrate 21 made of GaAs, and an n-type Ga
An external collector layer 20 made of As, and a semi-insulating Ga As layer formed in order on this external collector layer 20.
A spacer layer 30 consisting of a spacer layer 30 and a thick external base layer 27 consisting of n-type GaAs, and a tapered insulating layer 25 whose thickness increases sequentially toward the base layer on the mesa side wall. A mesa-shaped emitter layer 24 made of n-type A/GaAs is formed to be embedded in the outer base layer 27 and a spacer layer 30 surrounded by the edge of the tapered insulating layer 25. A true base layer 23 made of n-type GaAs, a true collector layer 22 made of n-type GaAs, and a mesa-shaped emitter layer 24 . External base layer 27 and external collector layer 20
Emitter electrodes 26 . It includes a base electrode 28 and a collector electrode 29. According to this embodiment, as in the previous embodiment, the emitter-base junction capacitance C in the veracity region can be reduced without causing a decrease in the mutual conductance g.
In addition to reducing Bt and base resistance Ra, it is also possible to reduce the base-collector parasitic capacitance JICbc in the external base region and the base-collector junction capacitance M and Cnc in the veracity region, making its high-speed and high-frequency characteristics more noticeable. It is possible to improve.

Figures 3(a) to (e) show the heterojunction bipolar structure of the present invention.
1 is a process sequence diagram showing one embodiment of a method for manufacturing a transistor. According to this embodiment, an HBT having the structure shown in FIG. 1 can be obtained. First, as shown in FIG. 3(a), GaAs
A donor (for example, S
i) Collector layer 12 made of n-type GaAs not doped with
and n-type Ga without doping with acceptor (e.g. Be)
The outer base layer 17 made of As has a thickness of 0.5 to 1.
0) tm and 0.1 to 0.5 μm using molecular beam epitaxial growth or organometallic pyrolysis vapor phase growth, respectively, and then a silicon oxide film (S
A mask pattern 31 made of an insulator such as iOz) or a silicon nitride film (Si3N4) is formed so that its opening is substantially perpendicular to the substrate. Next, Figure 3(b)
As shown in FIG. 3, the external base 17 is selectively etched through the mask pattern 31 to form an opening so that a bottom thickness of about 0.03 to 0.2 μm remains. A suitable etching method is a reactive ion etching method using an atmospheric gas such as boron chloride (BCl) gas or chlorine (C12) gas, or a reactive ion beam etching method, which provides a nearly vertical etched cross section. be.

Here, a tapered insulating layer 15 is formed so as to cover the side wall surface of the opening of the external base layer 17.

This insulating layer 15 can be easily formed by the following procedure. That is, first, for example, a silicon oxide film (Si02) is formed on the entire surface of the substrate using a film forming method having good step coverage such as chemical vapor deposition, and then, for example,
Using an anisotropic etching method such as reactive ion etching in a carbon tetrafluoride (CF) gas atmosphere, an unnecessary silicon oxide film (Si02
) can be selectively removed by etching. Next, as shown in FIG. 3(C), the bottom of the opening of the external base 17 is selectively etched away using the mask pattern 31 and the tapered insulating layer 15 as a mask to remove the lower collector layer 1.
Expose the surface of 2.

Next, as shown in FIG. 3(d), a solid base layer 13 made of p-type GaAs is formed on the exposed surface of the collector layer 12.
Next, a mesa-shaped emitter layer 1 made of n-type AffGaAs is formed.
4 are epitaxially grown until at least the side walls of the tapered insulating layer 15 are covered. For the epitaxial growth of the solid base layer 13 and mesa-shaped emitter layer 14, a highly selective growth method typified by metal organic pyrolysis vapor phase epitaxy is suitable.

Finally, as shown in FIG. 3(e), a metal that exhibits ohmic contact with n-type GaAs, such as A u G
An emitter electrode 16 made of e/Ni is formed to cover the exposed portion of the emitter layer 14, and the mask layer pattern 31 and the external base layer 17 are partially etched using well-known methods to form the external base layer 17 and the external base layer 17. Each predetermined region on the collector layer 12 is exposed, and a metal, for example, Au, which exhibits ohmic contact with n-type GaAs is
Collector electrode 19 and p made of Ge/Ni
The HBT of the present invention having the structure shown in FIG. 1 is completed by forming base electrodes 18 made of a metal exhibiting ohmic contact with the GaAs type, such as AuZn, AuCr, AuMn, etc.

FIGS. 4(a) to 4(e) are process flow diagrams showing an embodiment of another method for manufacturing a heterojunction bipolar transistor of the present invention. According to this embodiment, an HBT having the structure shown in FIG. 2 can be obtained.

First, as shown in FIG. 4(a), an external collector layer 20 made of n-type GaAs doped with a donor (for example, St) is placed on a semi-insulating semiconductor substrate 21 made of GaAs. A spacer layer 30 made of semi-insulating GaAs and an acceptor (
For example, the external base layer 27 made of p-type GaAs doped with Be) is coated with a thickness of 0.5 to 1.0 .mu.m and a thickness of 0.5 to 1.0 .mu.m, respectively.
Silicon oxide film (Si02) and silicon nitride are grown sequentially to thicknesses of 3 to 1.0 μm and 0.1 to 0.5 μm using molecular beam epitaxial growth or metal-organic pyrolysis vapor phase growth, etc. A mask pattern 31 made of an insulator such as a film (Si3N4) is formed so that the opening is substantially perpendicular to the substrate. Next, Figure 4 (b
), the external base layer 27 is selectively etched through the mask pattern 31 until the bottom thickness is 0.0.
The opening is made so that about 3 to 0.2 μm remains. Here, a tapered insulating layer 25 is formed so as to cover the side wall surface of the opening of the external base layer 27. The method of etching the external base 27 and the method of forming the tapered insulating layer 25 are carried out in the same manner as described in FIG. 2(b) of the previous embodiment. Next, as shown in FIG. 4C, the bottom of the opening of the external base 27 and the spacer layer 30 are etched away using the mask pattern 31 and the tapered insulating layer 25 as masks, and the surface of the lower external collector layer 20 is removed. expose.

Next, as shown in FIG. 4(d), the outer collector layer 20
A true collector layer 22 made of n-type GaAs is formed on the exposed surface of the
until it reaches the upper surface of the spacer layer 30, and the p-type Ga
The solid base layer 23 made of As is further made of n-type AfGaA.
The mesa emitter layer 2-4 consisting of S is at least an insulating layer 25.
Epitaxial growth is performed until the side walls of each are covered. These true collector layers 22. For the epitaxial growth of the solid base layer 23 and the mesa emitter layer 24, a highly selective growth method typified by metal organic pyrolysis vapor phase epitaxy is suitable.

Finally, as shown in FIG. 4(e), a metal that exhibits ohmic contact with n-type GaAs, such as A u G e
An emitter electrode 26 of /Ni is formed over the exposed portion of the mesa emitter layer 24, and the mask pattern 31 and the extrinsic base layer 27 are partially etched using well-known methods to form the extrinsic base layer. 27 and the external collector layer 20 are exposed, and the n-type G
Metals that exhibit ohmic contact with aAs, for example,
Collector electrode 29 made of AuGe/Ni
By forming base electrodes 28 made of a metal exhibiting ohmic contact with n-type GaAs and n-type GaAs, for example, AuZn, AuCr, AuMn, etc., the second
The HBT of the present invention having the structure shown in the figure is completed. Note that semi-insulating GaAs containing donor or acceptor impurities forming a deep energy level is used for the spacer layer 30, but it is also possible to use GaAs made of a true semiconductor not doped with impurities. . This material functions as a semi-insulating material exhibiting a resistivity of about 108 Ω■ at room temperature. Furthermore, it is also possible to use an insulating material such as calcium fluoride that has lattice matching with GaAs and can be epitaxially grown.

Figures 5(a) to (e) show the heterojunction bipolar structure of the present invention.
FIG. 7 is a process sequence diagram showing an example of another method for manufacturing a transistor. According to this embodiment, the second
An HBT having the structure shown in the figure can be obtained. First, Figure 5 (a
), n-type GaA doped with a donor (for example, St) is placed on a semi-insulating semiconductor substrate 21 made of GaAs.
an external collector layer 20. Suspension layer 30 made of semi-insulating GaAs. and an acceptor (e.g. Be)
The external base layer 27 made of n-type GaAs doped with
A silicon oxide film (SiO2) is grown sequentially to a thickness of m and 0.1 to 0.5 μm using molecular beam epitaxial growth or metal-organic pyrolysis vapor phase growth.
Alternatively, a mask pattern 31 made of an insulator such as silicon nitride film (Si3N4) is formed so that the opening is substantially perpendicular to the substrate. Next, as shown in FIG. 5(b), the external base layer 2 is coated through the mask pattern 31.
7 is selectively etched so that the bottom thickness is 0.03 to 0.
．． The opening is made so that about 2 μm remains. Here, a tapered insulating layer 25 is formed so as to cover the side wall surface of the opening of the external base layer 27. The method of etching the external base layer 27 and the method of forming the tapered insulating layer 25 are carried out in the same manner as described above. Next, Figure 5 (C)
As shown in FIG. 3, Si ions, for example, are implanted from the surface side of the substrate 21 using the mask pattern 31 and the tapered insulating layer 25 as masks, and are activated by heat treatment to form a true material having n-type conductivity in the spacer layer 30. sex collector layer 22
form. The ion implantation conditions at this time are, for example, if the thickness of the spacer layer 30 is 0.5 μm, the Si ions are implanted at a dose of 2×1012 cm−2 and an acceleration energy of 2
It is sufficient to inject at 80 Key and heat treat at 800° C. for 5 seconds. This results in approximately 5 x 1016
An n-type true collector layer 22 having a carrier concentration of cm-' can be formed. Then, using the mask pattern 31 and the tapered insulating layer 25 as a mask, the bottom surface of the opening in the external base layer 27 is selectively etched away to expose the surface of the collector layer 22 below.

Next, as shown in FIG. 5(d), a true base layer 23 made of n-type GaAs is formed on the exposed surface of the collector layer 22, and then a mesa-shaped emitter layer 24 made of n-type AJGaAs is formed as at least an insulating layer. Epitaxial growth is performed until the side walls of 25 are covered. For the epitaxial growth of the solid base layer 23 and mesa-shaped emitter layer 24, a highly selective growth method typified by metal organic pyrolysis vapor phase epitaxy is suitable.

Finally, as shown in FIG. 5(e), the emitter voltage [! 26. By forming the base electrode 28 and the collector electrode 29, the HBT of the present invention having the structure shown in FIG. 2 is completed.

In the above explanation, the external base layer 17 (or 27) is entirely formed of a single layer of n-type GaAs, but using the mask pattern 31, the region to be etched away is formed of p-type GaAs.
s, the region to remain may have a two-layer structure made of p-type Aj'GaAs. With this two-layer structure, CC
Only the p-type GaAs region can be selectively etched away by reactive etching in a mixed gas atmosphere of e2F2 and He. Therefore, the region where the tapered insulating layer 15 (or 25) is to be formed, the integrity base layer 13 (or 23) and the outer base layer 17 (or 2
7) It becomes possible to accurately control the contact area with

〔Effect of the invention〕

As described in detail above, according to the present invention, the true base layer or the true base layer and the collector layer in a transistor are located at the wall edge of the tapered insulating layer provided on the mesa side wall of the emitter layer. Since the respective sizes are defined, the base-emitter junction area and the base-collector junction area are each miniaturized. Therefore, the contact area between the emitter layer and the emitter electrode can be formed larger than the base-emitter junction area, and the base-emitter capacitance CBE can be increased without increasing the emitter resistance, that is, without reducing the mutual conductance g. can be significantly reduced, so the current gain cutoff frequency ft
can be significantly improved. In addition, the base-collector junction capacitance CBE is also reduced, and the base resistance RB and base-collector parasitic capacitance cbo of the external base region are also reduced by thickening the external base layer and inserting a spacer layer between the external base layer and the external collector layer. Since the upper limit value of the maximum oscillation frequency f wax can be significantly increased, it is possible to have an extremely significant effect on improving the high-speed and high-frequency characteristics of the HBT.

Further, according to the manufacturing method of the present invention, the HBT of the present invention can be manufactured and provided using ordinary process technology, and therefore, the reliability can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 shows an npn-type AI! Ga
Chip cross-sectional view of A s / Ga As heterojunction pi, polar transistor, FIG. 2 shows another embodiment of the present invention, npn type AI Ga As / G
aA sChip cross-sectional view of a heterojunction bipolar transistor, FIGS. 3(a) to (e) are process flow diagrams showing an embodiment of the method for manufacturing the inventive heterojunction bipolar transistor, FIGS. 4(a) to 4(e). (e) is a process sequence diagram showing an embodiment of another method for manufacturing the heterojunction bipolar transistor of the present invention, and FIGS. 5(a) to (e) show another method for manufacturing the heterojunction bipolar transistor of the present invention. A process sequence diagram showing one embodiment, FIG. 6, is a conventional npn type AI!
1 is a chip cross-sectional view showing the structure of a GaAs/GaAs heterojunction bipolar transistor. FIG. 11.21...GaAs semi-insulating semiconductor substrate, 12-
...Collector layer (n-GaAs), 13.23... Verity base layer, 14.24... Mesa-shaped emitter layer (n-GaAs)
-AffGaAs), 15.25-Tapered insulating layer, 16.26... Emitter electrode, 17°27... External base layer, 18.28... Base electrode, 19.29
... Collector electrode, 30 ... Spacer layer (semi-insulating GaAs), 31 ... Mask pattern (Si02)
.

Claims (5)

[Claims] (1) A semi-insulating semiconductor substrate, a collector layer formed on the substrate, a thick external base layer laminated on the collector layer, and a film thickness sequentially formed on the mesa sidewall toward the base layer. a mesa-shaped emitter layer comprising an increasing tapered insulating layer and formed embedded within the thick-film external base layer; and an external base surrounded by an edge of the tapered insulating layer of the mesa-shaped emitter layer. A heterojunction comprising: a true base layer formed in the plane of the layer; and an emitter electrode, a base electrode, and a collector electrode provided on the upper surfaces of the mesa-shaped emitter layer, the external base layer, and the collector layer, respectively. Bipolar transistor. (2) a step of sequentially epitaxially growing a collector layer and a thick external base layer on a semi-insulating semiconductor substrate, and a selective etching step of forming a groove of a predetermined depth on the thick external base layer; selectively forming a tapered insulating layer on the side wall surface in the groove of the external base layer, the thickness of which increases sequentially toward the base layer; and forming the external base layer on the bottom of the groove using the pattern of the tapered insulating layer as a mask. a selective epitaxial growth step of forming a solid base layer on the exposed surface of the collector layer in the trench; forming a mesa-shaped emitter layer on the solid base layer, selectively epitaxially growing an emitter layer along sidewall surfaces of the layer;
A method for manufacturing a heterojunction bipolar transistor, comprising the step of forming an emitter electrode, a base electrode, and a collector electrode on the upper surfaces of the mesa-shaped emitter layer, external base layer, and collector layer, respectively. (3) A semi-insulating semiconductor substrate, an external collector layer formed on the substrate, a spacer layer made of a semi-insulating material or an insulating material, and a thick film external base formed on the external collector layer in sequence. a mesa-shaped emitter layer, the mesa-shaped emitter layer having a tapered insulating layer on a sidewall of the mesa, the thickness of which increases sequentially toward the base layer, and being embedded in the thick external base layer; a true base layer and a true collector layer respectively formed in the plane of an outer base layer and a spacer layer surrounded by the edge of the tapered insulating layer of the mesa-shaped emitter layer, the outer base layer and the outer A heterojunction bipolar transistor comprising an emitter electrode, a base electrode, and a collector electrode, each provided on an upper surface of a collector layer. (4) A step of sequentially epitaxially growing an external collector layer, a spacer layer made of a semi-insulating semiconductor material or an insulating material, and a thick external base layer on a semi-insulating semiconductor substrate, and forming a predetermined depth on the external base layer. a selective etching step for forming a groove portion; a step for selectively forming a tapered insulating layer whose thickness increases sequentially toward the base layer on a side wall surface within the groove portion of the external base layer; and the tapered insulating layer pattern. a selective etching step of the external base layer and spacer layer of removing the external base layer and spacer layer on the bottom surface of the trench until the lower collector layer is exposed using the mask as a mask; a selective epitaxial growth step of sequentially forming a solid collector layer and a solid base layer; and a mesa-shaped emitter layer on the solid base layer, selectively epitaxially growing an emitter layer along the sidewall surface of the tapered insulating layer. and a lead electrode forming step of forming an emitter electrode, a base electrode, and a collector electrode on the upper surfaces of the mesa-shaped emitter layer, the external base layer, and the external collector layer, respectively. Method of manufacturing transistors. (5) selectively etching the external base layer using the pattern of the tapered insulating layer as a mask to remove the external base layer at the bottom of the groove until the spacer layer below is exposed; and the exposed surface of the spacer layer in the groove. forming a true collector layer by ion implantation, ion-implanting impurities using the tapered insulating layer pattern as a mask;
5. The method of manufacturing a heterojunction bipolar transistor according to claim 4, further comprising a selective epitaxial growth step of forming a transparent base layer on the transparent collector layer.