JPH0618206B2 - Method for manufacturing heterojunction bipolar transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a heterojunction bipolar transistor using a heterojunction such as a compound semiconductor.

[Conventional technology]

2. Description of the Related Art In recent years, active research and development have been conducted on semiconductor devices toward higher integration and higher speed. In particular, bipolar transistors using heterojunctions such as compound semiconductors (hereinafter,
HBT) has high emitter injection efficiency, high gain and high speed, and is attracting attention as a next-generation semiconductor device. This HBT is a molecular beam epitaxial growth method,
With the progress of thin-film multi-layer crystal growth technology for compound semiconductors, such as metalorganic pyrolysis vapor phase epitaxy, this has become possible.

In this HBT, the maximum oscillation frequency f _max, which is one index indicating the high speed / high frequency characteristics, is expressed by the following equation.

Where f _T is the current gain cutoff frequency, R _B is the base resistance, C _BC is the base-collector junction capacitance in the intrinsic region of the transistor, C _bc is the base-collector parasitic capacitance in the external base region of the transistor, and g _m is the transistor C _BE is the base of the intrinsic region of the transistor
It is the emitter capacitance.

As is clear from the above equation, as one means for realizing high-speed operation of the HBT, the base-collector junction capacitance C _BC , the base-collector parasitic capacitance C _bc , and the base-emitter capacitance C _BE.
Alternatively, it is necessary to make the base resistance R _B as small as possible.
Conventionally, in order to realize this high-speed operation, by miniaturizing the intrinsic region of the transistor, the base-collector junction capacitance C _BC and the base-emitter capacitance C _BE are reduced and the transistor external base region is selectively formed. By implanting oxygen or hydrogen ions with high energy and semi-insulating the base-collector junction, the base-collector parasitic capacitance _Cbc is reduced. In addition to these methods, a base contact layer having the same conductivity type as the base layer and having a high concentration of impurities is formed in the external base region by an ion implantation and heat treatment process to reduce the sheet resistance of the external base layer and the base layer. The base resistance R _B is reduced by reducing the contact resistance with the electrode.

FIG. 2 shows a sectional view of a conventional HBT using GaAs / AlGaAs as a heterojunction.

On the semi-insulating substrate 21, a collector layer 22 made of n-type GaAs, a base layer 26 made of p-type GaAs, and n-type AlG.
An emitter layer 27 made of aAs is formed. The base layer 26 and the collector layer 22 immediately below the emitter layer 27
Constitutes the intrinsic region of the transistor and is responsible for the actual transistor operation. In the area outside this intrinsic area,
Mask previously provided on the emitter layer 27 (not shown)
Oxygen ions and p from the surface of the substrate by utilizing
Ion-implanted insulating layer 2 is formed by sequentially ion-implanting a dopant (eg, Mg) that forms type conductivity and heat-treating.
11 and p-type GaAs base contact layer 2
12 are formed. With this configuration, the base-collector parasitic junction capacitance C _bc in the external region of the intrinsic region
And the sheet resistance of the base / contact layer 212 and the contact resistance with the base electrode 29 are simultaneously reduced to reduce the base resistance R _B.

[Problems to be solved by the invention]

In such a conventional HBT, since the intrinsic region of the transistor is defined by the mask provided on the emitter layer 27, miniaturization of the intrinsic region is limited by the lithography technique when forming this mask. .
That is, in the current photolithography technology, 1 μm or less, and in the electron beam lithography technology, 0.5 μm or less.
It is difficult to form the following fine mask with good reproducibility. Therefore, there is a limit in reducing the base-emitter capacitance and the base-collector junction capacitance in the intrinsic region.

Further, the ion implantation step and the heat treatment step associated therewith for forming the ion-implanted insulating layer 211 and the base contact layer 21 induce crystal defects in the base contact layer 212 and the impurities in each layer of the transistor are adjacent to each other. Had diffused into layers. That is, the crystal defects of the base contact layer 212 cause the trapping of carriers and prevent the base resistance from being sufficiently reduced. In addition, diffusion of impurities, especially impurities in the base layer 26 causes
Diffused into the GaN layer, resulting in an increase in the recombination current, which significantly reduced the emitter injection efficiency. Moreover, even with such ion implantation, the base contact layer 212 and the collector layer 22 still face each other, so that the base-collector parasitic capacitance C _bc is at most 30%.
It was possible to reduce only about 40%.

An object of the present invention is to eliminate the need for an ion implantation step for inducing the above problems, and to provide a base-emitter capacitance and a base-collector junction capacitance, a base resistance, a base
It is an object of the present invention to provide a method for manufacturing a heterojunction bipolar transistor capable of significantly reducing the collector parasitic capacitance.

[Means for solving problems]

A method of manufacturing a heterojunction bipolar transistor according to the present invention comprises a step of forming a collector layer made of a first semiconductor material on a semi-insulating semiconductor substrate, a mask having a predetermined pattern on the collector layer, and a side surface of the mask. Forming a side wall of the collector layer by using the mask and the first side wall to etch a part or all of the exposed portion of the collector layer to define a spacer region; and insulating on the etched surface. A spacer layer made of a material or a semi-insulating semiconductor material and a base contactor layer made of a second semiconductor material on the spacer layer in order to backfill the spacer region by epitaxial growth, and etching the first sidewall. A step of exposing the collector layer, and a third step of exposing the base contact layer and the collector layer.
Of epitaxially growing a base layer made of a semiconductor material and an emitter layer made of a fourth semiconductor material, forming a second side wall on the exposed side surface of the mask, and using the mask and the second side wall. Then, the exposed portion of the emitter layer is selectively etched away or insulated.

[Work]

In the present invention, the junction region between the collector layer and the base layer and the junction region between the base layer and the collector layer are defined by the first side wall and the second side wall, respectively. , The base-collector junction capacitance C _BC and the base-emitter capacitance C _BE in the intrinsic region can be significantly reduced.

Furthermore, in the present invention, the collector layer immediately below the external base region is etched, and a spacer layer made of an insulating material or a semi-insulating semiconductor material is formed in this etched region by epitaxial growth. Base-collector parasitic capacitance C depending on thickness
_bc greatly reduced or the collector layer is etched,
By forming the spacer layer directly on the semi-insulating semiconductor substrate, the base-collector parasitic capacitance _Cbc can be made almost zero.

Further, in the external base region, since the base contact layer made of the semiconductor material shown in FIG. 2 is formed by the epitaxial growth method, the base resistance can be significantly reduced by adjusting the doping concentration or the thickness of the base contact layer. .

Moreover, since each of these layers is formed by the epitaxial growth method, it is possible to prevent the induction of crystal defects and the diffusion of impurities without the need for the ion implantation step and the heat treatment step accompanying it.

〔Example〕

Hereinafter, the npn-type AlGaAs / GaAs HBT of the present invention
Will be described as an example with reference to the drawings.

1 (a) to 1 (e) are sectional views of an element for explaining one embodiment of the present invention in the order of manufacturing steps. First,
As shown in FIG. 1A, an n-type G doped with a donor (for example, Si) on a semi-insulating substrate 11 made of GaAs.
After the collector layer 12 made of aAs is grown to have a thickness of 0.5 μm to 1.0 μm by a molecular beam epitaxial growth method, a metal organic thermal decomposition vapor deposition method, or the like, Si
It is made of an insulator such as O ₂ and Si ₃ N _4, and has a thickness of 1.0 μm to 2.
A mask 13 of about 0 μm is formed. This is, for example,
If the mask 13 is Si ₃ N ₄ , processing by reactive ion etching in a mixed gas of CF ₄ + O ₂ or SF ₆ gas can be realized. Next, the insulating first side wall 14 made of a material different from that of the mask 13 is formed on the side surface of the mask 13. The formation of the first side wall 14 is performed by the following procedure. First, if the mask 13 is made of Si ₃ N ₄ , for example, SiO ₂ is formed on the entire surface of the substrate by using a film forming method with good step coverage such as chemical vapor deposition. Then, SiO ₂ deposited on the flat portion of the substrate is selectively removed by etching using an etching method having anisotropy in the etching progress direction such as reactive ion etching in a CF ₄ gas atmosphere. Side walls 14 are formed.

Next, as shown in FIG. 1B, the collector layer 12 is etched using the mask 13 and the first side wall 14 as a mask to define the spacer region. In the case of the present embodiment, the exposed portion of the collector layer 12 is entirely etched to remove the semi-insulating substrate 11.
Is exposed. As the etching means, reactive ion etching or reactive ion beam etching using an atmosphere gas such as BCl ₃ or Cl ₂ that can obtain a substantially vertical etching section is suitable. After that, a donor impurity (for example, oxygen) that forms a deep energy level with the same material as the semi-insulating substrate 11 on the exposed surface of the semi-insulating substrate 11
Alternatively, a spacer layer 15 made of GaAs that is semi-insulated by doping with acceptor impurities (eg, Cr, Fe), and then a high concentration of the acceptor (eg, Be) (eg, 4 × 10 4) is formed on the spacer layer 15. ^The base contact layer 16 made of p-type GaAs doped to ^{19 to} 10 × 19 ¹⁹ cm ⁻³ ) is sequentially epitaxially grown until the upper surface of the collector layer 12 is reached, and the spacer region is backfilled. For the epitaxial growth of the spacer layer 15 and the base contact layer 16, a highly selective growth method typified by a metal organic thermal decomposition vapor phase growth method is suitable.

Subsequently, as shown in FIG. 1C, the first side wall 14 is selectively etched to expose the collector layer 12. For this etching, if the first side wall 14 is SiO ₂ and the mask 13 is Si ₃ N ₄ , for example, buffered hydrofluoric acid is suitable. After that, an acceptor (eg, Be) -doped p layer is formed on the collector layer 12 and the base contact layer 16.
N-type AlGaAs, n-type GaAs, and n-type InG in which a base layer 17 made of n-type GaAs is doped with a donor (for example, Si) with a thickness of several tens nanometers to several hundreds nanometers.
The emitter layer 18 made of a laminated body of aAs is sequentially and selectively grown epitaxially to a thickness of several hundred nanometers. At this time, the thickness of each of these layers is set so that the side surface of the mask 13 is exposed to about 0.5 μm to 1.0 μm.

Next, as shown in FIG. 1D, a second sidewall 112 made of a metal (for example, W, Mo, etc.) that makes ohmic contact with the emitter layer 18 is formed on the side surface where the mask 13 is exposed. Similar to the method of forming the first side wall 14, for example, W is formed on the entire surface of the substrate by using a film forming method with good step coverage such as a chemical vapor deposition method using an organic metal as a raw material. rear,
It is formed by selectively removing W deposited on the flat portion of the substrate by using an etching method having anisotropy in the etching progress direction, for example, reactive ion etching in a CF ₄ gas atmosphere. The thickness of the second side wall 112 is preferably set to be the same as the thickness of the first side wall 14.
The second sidewall 112 in this case functions as an emitter electrode. After that, the exposed portion of the emitter layer 18 is removed by etching using the mask 13 and the second sidewall 112 as a mask to expose the base layer 17. Therefore, the junction region of the base layer 17 and the emitter layer 18 in the intrinsic region of the transistor is defined by the thickness of the second sidewall 112.

Next, as shown in FIG. 1 (e), the mask 13 is partially etched by a known method to expose a predetermined region of the collector layer 12 where an electrode is to be formed, and ohmic contact with n-type GaAs is performed. Electrode 10 made of a conductive metal (for example, AuGe / Ni) and an ohmic contact metal (for example, AuZn, AuCr, A) with respect to p-type GaAs.
a base electrode 111 composed of
Is completed.

In this embodiment, the spacer layer 15 is made of semi-insulating GaAs containing a donor or acceptor impurity that forms a deep energy level. However, GaAs made of an intrinsic semiconductor not doped with impurities is used. Is also good.
This is 10 ⁸ Ω. It functions as a semi-insulating material with a resistivity of about cm. Further, an insulating material such as calcium fluoride, which is lattice-matched with GaAs and is capable of epitaxial growth, may be used as the spacer layer.

Further, in the present embodiment, since the second side wall 112 made of metal such as W and Mo makes ohmic contact with the emitter layer 18,
The uppermost layer of the emitter layer 18 is composed of n-type InGaAs, but contains a high concentration of donors (for example, 1 × 10 ¹⁹ cm ^−3).
It is also possible to use n-type GaAs doped as described above. or,
As another method of forming the second side wall 112, a metal that makes ohmic contact with the emitter layer is formed by vapor deposition or sputtering, and then an insulating side wall such as SiO ₂ is formed in the same manner as the first side wall. The exposed portion of the metal may be removed by etching using the insulating sidewall as a mask. That is,
In this case, the second side wall 112 has a two-layer structure of an emitter electrode and an insulating side wall.

Further, in this embodiment, the junction region between the base layer 17 and the emitter layer 18 is defined by etching away the exposed emitter layer 18 using the second sidewall 112 as a mask. With the mask as a mask, the exposed emitter layer 18 may be selectively ion-implanted with hydrogen, oxygen or the like to insulate the emitter layer 18.

〔The invention's effect〕

As described above, in the present invention, the junction area of the base-collector and the junction area of the base-emitter in the intrinsic region of the transistor are defined by the thickness of the first side wall and the second side wall, respectively. It is possible to easily form a bonding region of order or sub-quarter micron order.

Further, in the external base region, since the spacer layer made of an insulating material or a semi-insulating semiconductor material can be formed on the semi-insulating substrate, the base layer or the base contact layer and the collector layer do not directly contact or face each other. be able to. Further, since this base contact layer is formed by epitaxial growth, it can be set to have a high concentration and a sufficient thickness.

Therefore, according to the present invention, the base resistance, the base-collector parasitic capacitance, and the base-emitter capacitance and the base-collector junction capacitance in the intrinsic region of the transistor can be significantly reduced, so that the operating frequency of the HBT can be greatly improved.

Moreover, since the ion implantation and the heat treatment step associated therewith are not required, it is possible to prevent the emitter implantation efficiency from being lowered due to the impurity diffusion.

[Brief description of drawings]

1 (a) to 1 (e) are cross-sectional views of an element for explaining an embodiment of the manufacturing method of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing an example of a conventional heterojunction bipolar transistor. . 11, 21 ... Semi-insulating substrate, 12, 22 ... Collector layer, 13 ... Mask, 14 ... First sidewall, 15 ... Spacer layer, 16,212 ... Base contact layer, 1
7, 15 ... Base layer, 18, 27 ... Emitter layer, 2
8 ... Emitter electrode, 110, 210 ... Collector electrode, 111, 29 ... Base electrode, 112 ... Second side wall, 211 ... Ion-implanted insulating layer.

Claims (2)

[Claims] 1. A step of forming a collector layer made of a first semiconductor material on a semi-insulating semiconductor substrate, a mask having a predetermined pattern on the collector layer, and a first side surface of the mask.
Forming a side wall of the collector layer, etching a part or all of the exposed portion of the collector layer to define a spacer region using the mask and the first side wall, and insulating material on the etched surface. Alternatively, a spacer layer made of a semi-insulating semiconductor material and a base contactor layer made of a second semiconductor material are sequentially epitaxially grown on the spacer layer to backfill the spacer region;
A side wall of the substrate is exposed to expose the collector layer, and a base layer made of a third semiconductor material and an emitter layer made of a fourth semiconductor material are sequentially epitaxially grown on the exposed portions of the base contact layer and the collector layer. A step of forming a second sidewall on the exposed side surface of the mask, and selectively etching away the exposed portion of the emitter layer by using the mask and the second sidewall, or insulating the exposed portion. A method of manufacturing a heterojunction bipolar transistor, comprising: 2. The method for manufacturing a heterojunction bipolar transistor according to claim 1, wherein at least a surface of the second side wall which is in contact with the emitter layer is made of a metal which makes ohmic contact with the emitter layer. .