JPH0620075B2 - Method for manufacturing heterojunction bipolar transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a heterojunction bipolar transistor using a heterojunction such as a compound semiconductor.

[Conventional technology]

2. Description of the Related Art In recent years, active research and development have been conducted on semiconductor devices toward higher integration and higher speed. In particular, a bipolar transistor (hereinafter referred to as H
BT) has high emitter injection efficiency, high gain and high speed, and is attracting attention as a next-generation semiconductor element. This HBT can be realized with the progress of thin film multi-layer crystal growth technology of compound semiconductors by the molecular beam epitaxial growth method, the organometallic pyrolysis vapor phase growth method and the like.

In this HBT, the maximum oscillation frequency f _max, which is one index indicating high speed and high frequency characteristics, is expressed by the following equation.

Here, f _T is the current gain cutoff frequency, R _B is the base resistance, C _BC is the base-collector junction capacitance in the intrinsic region of the transistor, and C _bc is the base-collector parasitic capacitance in the external region of the transistor.

As is clear from the equation (1), as one means for realizing the high speed operation of the HBT, the base-collector parasitic capacitance C
_It is necessary to make _bc or base resistance R _B as small as possible. Conventionally, in order to realize this high-speed operation, oxygen ions are selectively implanted with high energy from the surface side of the substrate to the external base region with respect to the substrate on which the transistor is formed,
By semi-insulating the base-collector junction, the base-collector parasitic capacitance C _bc is reduced, and a dopant forming the same conductivity type as that of the base is ion-implanted into these external base regions, followed by heat treatment. To activate the dopant to reduce the sheet resistance of the external base layer and the contact resistance with the base electrode formed thereafter, thereby reducing the base resistance R _B.

FIG. 2 shows a sectional view of a conventional HBT chip using GaAs / AlGaAs as a heterojunction.

On the semi-insulating substrate 21, a collector layer 22 made of n-type GaAs, a base layer 26 made of p-type GaAs, and n-type AlG.
An emitter layer 27 made of aAs is formed. The base layer 26 and the collector layer 2 immediately below the emitter layer 27
2 constitutes the intrinsic region of the transistor and is responsible for the actual transistor operation. In the region outside this intrinsic region, oxygen ions and a dopant (eg, Mg) that forms p-type conductivity are sequentially ion-implanted from the surface of the substrate and heat-treated, so that the ion-implanted insulating layer 211 and the p-type conductivity are formed. A base contact layer 212 made of GaAs is formed. With this configuration, the base-collector parasitic capacitance C _bc in the region outside the intrinsic region is reduced, the sheet resistance of the base contact layer 212 and the contact resistance with the base electrode 28 are simultaneously reduced, and the base resistance R is reduced. _B was reduced.

[Problems to be solved by the invention]

In such a conventional HBT, the oxygen ions implanted between the collector layer 22 and the base contact layer 212 and the p-type dopant implanted for the purpose of forming the base contact layer 212 are the base contact layer 212.
Induces a crystal defect. Since this crystal defect cannot be completely removed even by heat treatment, carriers in the base contact layer are trapped by this defect, and as a result, the base resistance R _B cannot be sufficiently reduced. In addition, the heat treatment process described above is performed by the impurities and the external base layer 212 that define the conductivity types of the base, emitter, and collector in the intrinsic region.
The impurity ion-implanted in the substrate was diffused into the adjacent layer, the impurity concentration distribution was changed, the recombination current increased, and the emitter implantation efficiency was significantly deteriorated.

Furthermore, the base-collector parasitic capacitance _Cbc can be reduced by at most 30% to 40% by such an ion implantation method.

An object of the present invention is to provide a method for manufacturing a heterojunction bipolar transistor which does not require an ion implantation step for inducing the above-mentioned problems and which has a significantly reduced base resistance and base-collector parasitic capacitance.

[Means for solving problems]

A method of manufacturing a heterojunction bipolar transistor according to the present invention comprises a step of forming a collector layer made of a first semiconductor material on a semi-insulating semiconductor substrate, a mask having a predetermined pattern is formed on the collector layer, and the mask is used. Etching the collector layer using the same to expose the semi-insulating semiconductor substrate, and selectively epitaxially growing an insulating material or a spacer layer made of a semi-insulating semiconductor material on the exposed semi-insulating semiconductor substrate. A step of epitaxially growing a base contact layer made of a second semiconductor material on the spacer layer; a step of partially etching an end of the mask near the spacer layer to expose the collector layer; A base layer made of a third semiconductor material and a fourth half on the exposed portions of the contact layer and the collector layer. It is configured and the step of successively epitaxially growing an emitter layer made of the body material.

[Action]

In the present invention, since the spacer layer made of the semi-insulating semiconductor material is formed by epitaxial growth directly on the semi-insulating semiconductor substrate immediately below the external base region, a structure in which the external base region and the collector layer do not oppose each other can be realized. . Therefore, the base-collector parasitic capacitance _Cbc can be made almost zero. Further, since the base contact layer made of the second semiconductor material is formed immediately below the external base region by the epitaxial growth method, the base resistance can be significantly reduced by adjusting the doping concentration and / or the thickness of the base contact layer. Moreover, since each of these layers is formed by the epitaxial growth method, it is possible to prevent the induction of crystal defects and the diffusion of impurities without requiring an ion implantation step and a heat treatment step accompanying it.

〔Example〕

Hereinafter, the present invention will be described with reference to npn type AlGaAs / GaAsHBT.
Will be described as an example with reference to the drawings.

1 (a) to 1 (e) are element cross-sectional views for explaining an embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 1A, a semi-insulating substrate 1 made of GaAs.
N-type GaA with a donor (eg, Si) topped on
The collector layer 12 made of s has a thickness of 0.5 μm to 1.0
After growth using molecular beam epitaxy or metal organic decomposition vapor deposition or the like _μm, SiO 2, S
A mask 13 having a predetermined pattern made of an insulator such as i ₃ N ₄ is formed.

Next, as shown in FIG. 1B, the collector layer 12 is removed by etching using a mask 13 to expose the semi-insulating substrate 11. As the etching means, reactive ion etching with an atmosphere gas such as BCl ₃ gas, Cl ₂ gas or the like, or a reactive ion beam etching, which can obtain a substantially vertical etching cross section, is suitable.

Then, as shown in FIG. 1 (c), in the exposed region of the semi-insulating substrate 11, the same material as that of the semi-insulating substrate 11 is used and a donor impurity (for example, oxygen) having a deep energy level or a deep energy level is used. Acceptor impurities (eg Cr,
GaAs semi-insulated by doping Fe)
Are epitaxially grown to reach the upper surface of the collector layer 12 to form a spacer layer 15. Further, a base contact layer 16 made of p-type GaAs doped with an acceptor (eg Be) at a high concentration (eg 4 × 10 ^{19 to} 10 × 10 ¹⁹ cm ⁻³ ) is epitaxially grown on the spacer layer 4. For the epitaxial growth of the spacer layer 15 and the base contact layer 16, a highly selective growth method typified by a metal organic thermal decomposition vapor phase growth method is suitable.

Subsequently, as shown in FIG. 1D, the end of the mask 13 facing the base contact layer 16 or the spacer layer 15 is selectively etched to expose the collector layer, and then the collector layer 12 is exposed. And p-type GaAs doped with acceptor (eg Be) on the base contact layer 16
The base layer 17 made of n is made to have a thickness of several tens of nanometers to several hundreds of nanometers, and the emitter layer 7 made of n-type GaAs doped with a donor (for example, Si) is epitaxially grown to a thickness of several hundreds nanometers.

Next, as shown in FIG. 1 (e), the mask 13 and the emitter layer 18 are partially etched by a known method to expose predetermined regions where electrodes on the collector layer 12 and the base layer 17 are to be formed. Then, an emitter electrode 19 and a collector electrode 110 made of an ohmic contact metal (for example, AuGe / Ni) for n-type GaAs, and an ohmic electrode 111 for p-type GaAs are formed to complete the HBT.

In the present embodiment, the semi-insulating GaAs containing a donor or acceptor impurity that forms a deep energy level is used for the spacer layer 15. However, GaAs made of an intrinsic semiconductor not doped with an impurity may be used. good.
This functions as a semi-insulating material that exhibits a specific resistance of about 10 ₈ [Ω · cm] at room temperature. Further, an insulating material which is lattice-matched to GaAs such as calcium fluoride and which can be epitaxially grown may be used as the spacer layer.

〔The invention's effect〕

As described above, in the present invention, the base contact layer and the base layer are epitaxially grown on the semi-insulating substrate via the spacer layer made of an insulating material or a semi-insulating semiconductor material. The layer and the collector layer do not face each other. Therefore, the base
The collector parasitic capacitance and the base resistance can be significantly reduced, and the operating frequency of the HBT can be greatly improved. Moreover, since the ion implantation and the heat treatment step associated therewith are not required, it is possible to prevent the emitter implantation efficiency from being lowered due to the impurity diffusion. Therefore, there is an effect that a heterojunction bipolar transistor that can operate at high speed and high frequency can be manufactured.

[Brief description of drawings]

1 (a) to 1 (e) are sectional views of an element for explaining one embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view showing an example of a conventional heterojunction bipolar transistor. 11, 21 ... Semi-insulating substrate, 12, 22 ... Collector layer, 13 ... Mask, 15 ... Spacer layer, 16, 21
2 ... Base contact layer, 17, 26 ... Base layer,
18, 27 ... Emitter layer, 19, 28 ... Emitter electrode, 110, 210 ... Collector electrode, 111, 29 ...
... base electrode, 211 ... ion-implanted insulating layer.

Claims (1)

[Claims] 1. A step of forming a collector layer made of a first semiconductor material on a semi-insulating semiconductor substrate, a mask having a predetermined pattern is formed on the collector layer, and the collector layer is etched using the mask. A step of exposing the semi-insulating semiconductor substrate, a step of selectively epitaxially growing a spacer layer made of an insulating material or a semi-insulating semiconductor material on the exposed semi-insulating semiconductor substrate, and on the spacer layer. A step of epitaxially growing a base contact layer made of a second semiconductor material; a step of partially etching an end of the mask near the spacer layer to expose the collector layer; and a step of forming the base contact layer and the collector layer. A base layer made of a third semiconductor material and an emitter layer made of a fourth semiconductor material are sequentially epitaxially formed on the exposed portion. Method of manufacturing a heterojunction bipolar transistor which comprises the step of Le growth.