JPH05198586A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a bipolar transistor of compound semiconductor in which parasitic capacitance between a base and a collector and between the base and an emitter are remarkably reduced and a method for manufacturing the same. CONSTITUTION:A bipolar transistor has a semiconductor laminated structure having at least a collector layer 3, a base layer 4 and an emitter layer 6 formed on a semi-insulating board 1. The base layer is removed or insulated in a region except an intrinsic base layer and an external base layer, and at least part of a base electrode 23 extended to the region is formed on an insulator layer 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and its manufacturing method.

[0002]

2. Description of the Related Art A bipolar transistor has an excellent feature that it has a larger current driving capability than a field effect transistor. Therefore, in recent years, not only Si but also Ga
Research and development of bipolar transistors using compound semiconductors such as As have been actively conducted. In particular, a bipolar transistor using a compound semiconductor has a great advantage in that the emitter / base junction can be configured as a heterojunction and the emitter injection efficiency can be largely maintained even if the base has a high concentration.

FIGS. 14A and 14B are a plan view and a sectional view of a semiconductor chip for explaining the structure of a conventional bipolar transistor.

This semiconductor chip comprises a semi-insulating substrate 1 made of GaAs, a collector contact layer 2 and a collector layer 3 made of n-GaAs, a base layer 4 made of p-GaAs, and a spacer layer made of an undoped GaAs layer. 5, an emitter layer 6 made of n-Al _0.25 Ga _0.75 As, and an n-Al _x Ga _1-x As layer (x: 0.25 → 0)
A graded layer 7 made of n-GaAs, an emitter contact layer 8 made of n-GaAs, an n-In _x Ga _1-x As graded layer (x: 0 → 0.5) 9, and an n-In _0.5 Ga layer.
_0.5 As layer 10, emitter electrode 30a made of AuGeNi, base electrode 23a made of AuMn, Au
The collector electrode 25 made of GeNi and the insulating region 21
, SiO ₂ films 12 and 26a, and AuMn layer 23c
And contact holes 32b, 32c and 32e. In FIG. 14A, the portion covered with only the SiO ₂ film 26a is drawn by a solid line.

Usually, the base layer is often set to have a thickness of 60 to 100 nm and a p-type impurity concentration of the order of 10 ¹⁹ cm ^{-3 in} order to operate a transistor at high speed. As the p-type impurity, for example, a molecular beam epitaxy method (hereinafter, ME
When the base layer is formed by the B method), Be,
When forming a base layer by a metal organic chemical vapor deposition method (hereinafter referred to as MOCVD method), C or Zn is often used. In FIG. 14B, the emitter / base junction is of a step junction type, but in addition to this, the Al composition x of the Al _x Ga _1-x As emitter layer is gradually changed in the emitter / base junction. Often used is a graded joint type. Further, the contact resistance can be reduced by forming the n-InGaAs layers 9 and 10 on the n-GaAs layer 8 as the emitter contact layer.

In FIG. 14A, the lead-out portion of the base electrode 23a formed outside the rectangular region 20 is formed on the insulated GaAs layer (base layer) 4. Similarly, the emitter layer 6 also has a lead portion, and that portion is formed on an insulated GaAs layer (emitter contact layer) protruding from a region surrounded by the intrinsic base layer and the external base layer. ..

15 to 17 are a plan view and a sectional view of a semiconductor chip, which are shown in the order of steps for explaining the method for manufacturing the above-described conventional bipolar transistor.

In this conventional example, first, as shown in FIG.
As shown in (b), a semi-insulating substrate 1 made of GaAs
N-GaAs layers 2 and 3, p-GaAs layer 4, undoped GaAs layer 5, n-Al _0.25 Ga _0.75 As layer 6, and n-Al _x Ga _1-x As layer (x: 0.25 → 0)
7, n-GaAs layer 8, and _{n-In x Ga 1-x} As
The layer (x: 0 → 0.5) 9 and the n-In _0.5 Ga _0.5 As layer 10 are sequentially formed by the MBE method, and then H ⁺ is injected into the other portion except the rectangular region 20 forming the bipolar transistor. Then, the insulating region 21 is formed.

Next, as shown in FIGS. 16 (a) and 16 (b),
After forming the AuGeNi layer and the SiO ₂ film 12 on the entire surface, a photoresist film (not shown) covering the rectangular region 13a is formed in order to define the emitter region and the emitter extraction region, and the SiO ₂ film 12 is used as a mask.
The emitter electrode 30a is formed by etching and removing the AuGeNi layer and the AuGeNi layer by reactive ion beam etching and ion milling, respectively. Then, after removing the above-mentioned photoresist film, the n-InGaAs layers 10, 9 and n are formed using the SiO ₂ film 12 as a mask.
-GaAs layer _{8, n-Al x Ga 1} -x As layer (x: 0.
25 → 0) 7, n-Al _0.25 Ga _0.75 As layer 6 and undoped GaAs layer 5 are removed by etching, and p-G
At the same time as exposing the aAs layer 4, an emitter layer is formed.
Furthermore, by implanting H ⁺ into the entire surface, the n-GaAs layer 3 immediately below the external base is insulated, and the parasitic capacitance between the external base and the collector is reduced.

Next, as shown in FIGS. 17 (a) and 17 (b),
Photoresist film having predetermined openings 22 (not shown)
After this is formed, the AuMn layer 23c is vapor-deposited from above using this as a mask and lift-off is performed to remove the photoresist film, whereby the base electrode 23a is formed in a self-aligned manner. Subsequently, a photoresist film (not shown) having a U-shaped opening 24 is formed, and p is used as a mask.
The -GaAs layer 4 and the n-GaAs layer 3 are removed by etching to expose the n-GaAs layer 2. Further, an AuGeNi layer of ohmic metal is vapor-deposited from above on the surface of the n-GaAs layer 2 by using this photoresist film as a mask, and then the photoresist film is dissolved in an organic solvent and lift-off is performed to form the collector electrode 25.

Next, after a SiO ₂ film 26a is formed on the entire surface and flattened, contact holes 32b, 32 are formed at predetermined locations.
c and 32e are provided, and these contact holes 32b, 3e are provided.
2c and 32e through the base electrode 23a,
Electrode pads (not shown) connected to the collector electrode 25 and the emitter electrode 30a are formed on the SiO ₂ film 26a to complete the compound semiconductor bipolar transistor as shown in FIGS. 14 (a) and 14 (b).

[0012]

The cutoff frequency f _T and the maximum oscillation frequency f _max of the bipolar transistor are

[0013]

[Equation 1]

Can be expressed as In equation (1), τ _E is the emitter time constant, τ _B is the base transit time, τ _C is the collector transit time, and τ _CC is the collector time constant. In equation (2), γ _b is the base resistance and C _BC is the base. -It is the capacity between collectors.

In equation (1), the emitter time constant τ _E and the collector time constant τ _CC are

[0016]

[Equation 2]

Where k is the Boltzmann constant, T
Is temperature, n is an ideal constant, q is the magnitude of electronic charge, I _C is collector current, C _BE is base-emitter capacitance, R _EE is emitter resistance, and R _C is collector resistance.

From the equation (2), the capacitance C between the base and the collector
_It can be seen that reducing _BC is very effective in increasing f _max . Further, it can be seen from the equations (1), (3) and (4) that the reduction of the base-collector capacitance is effective for increasing f _T.

The base-collector capacitance includes not only the intrinsic capacitance component associated with the intrinsic portion of the bipolar transistor but also the parasitic component such as the capacitance component associated between the external base and collector and the stray capacitance associated with the electrodes. Be done. In the conventional bipolar transistor, it is difficult to sufficiently reduce this parasitic capacitance, which is one of the major factors that hinder the speeding up and the frequency of the device.

Further, it is difficult to sufficiently increase the resistance and insulation of the high-concentration base layer and the high-concentration emitter contact layer having a carrier concentration of 10 ¹⁹ cm ⁻³ by ion implantation, and at the same time, the device manufacturing process A problem that carriers are recovered by heat treatment performed in the middle to deteriorate the insulating property is likely to occur. In this case, in the conventional bipolar transistor, there arises a problem that parasitic emitter-base capacitance is generated in the emitter electrode lead-out portion or f _T and f _max are reduced due to the increase in the base-collector parasitic capacitance. Will end up.

The object of the present invention is to solve these problems and significantly reduce the base-collector and base-emitter parasitic capacitances, thereby f _T and f _max.
It is an object of the present invention to provide a bipolar transistor having improved characteristics and a manufacturing method thereof.

[0022]

The bipolar transistor of the present invention comprises at least a collector layer on a semi-insulating substrate,
In a bipolar transistor in which a semiconductor laminated structure including a base layer and an emitter layer is formed, an intrinsic base layer is formed and formed in a first region, and an external base layer electrically coupled to the intrinsic base layer is a second region. And the base layer is removed in the third region excluding the first and second regions, and at least a part of the base electrode extracted to the third region is formed on the insulator layer. It has been done.

Further, in a bipolar transistor in which a semiconductor laminated structure including at least a collector layer, a base layer and an emitter layer is formed on a semi-insulating substrate, an intrinsic base layer is arranged and formed in the first region, and the intrinsic base layer is formed. An external base layer electrically coupled to the second region is formed and formed in the second region, the base layer is insulated in the third region except the first and second regions, and the third region is formed.
At least a part of the base electrode extracted to the region may be formed on the insulator layer.

However, the step difference between the external base layer and the insulator layer at the boundary between the second region and the third region may be smaller than the thickness of the base electrode.

Further, the emitter layer has the first region and the second region.
It may be arranged and formed inside the fourth region formed by the region.

The manufacturing method for realizing the bipolar transistor of the present invention as described above includes a collector contact layer made of at least a first semiconductor layer on a semi-insulating substrate,
Forming a semiconductor laminated structure including a collector layer made of the second semiconductor layer, a base layer made of the third semiconductor layer, an emitter layer made of the fourth semiconductor layer, and an emitter contact layer made of the fifth semiconductor layer; After sequentially forming a first conductor layer and a first insulator layer on the semiconductor laminated structure, a first mask having a predetermined pattern is formed on the first insulator layer. A step of sequentially removing a part of the first insulator layer, the first conductor layer, the fifth semiconductor layer and the fourth semiconductor layer by using a mask by etching until a predetermined thickness is obtained; After removing the first mask, a second mask having a predetermined pattern is formed, and using the second mask, the fourth semiconductor layer and the third semiconductor layer, or the fourth semiconductor layer. Semiconductor layer,
A step of removing a part of the third semiconductor layer and the second semiconductor layer by etching; and a step of removing the second mask to form a second insulator layer on the entire surface, and then performing the second step.
A third mask having a predetermined pattern is formed on the insulating layer, and the second insulating layer is removed by etching using the third mask to remove the fourth semiconductor layer and the fourth semiconductor layer. No. 5, the step of forming a side wall made of a second insulator layer on the side surfaces of the semiconductor layer, the first conductor layer and the first insulator layer, and the third mask is removed, and the first mask is removed.
And a portion of the fourth semiconductor layer or the fourth semiconductor layer and the third semiconductor layer is removed by etching using the second insulator layer as a mask, and then a predetermined amount is formed on the third semiconductor layer. Selectively forming a sixth semiconductor layer having a thickness of, and forming a fourth mask having a predetermined pattern, and using the fourth mask, the second semiconductor layer and the first semiconductor layer are formed. Insulating the layers, removing the fourth mask, and forming a base electrode having a predetermined pattern of a second conductor layer on the sixth semiconductor layer and the second insulator layer. It is characterized by including and.

On the semi-insulating substrate, at least a collector contact layer made of the first semiconductor layer, a collector layer made of the second semiconductor layer, a base layer made of the third semiconductor layer, and a fourth semiconductor layer. Forming a semiconductor laminated structure including an emitter contact layer composed of an emitter layer and a fifth semiconductor layer; forming a first conductor layer and a first insulator layer on the semiconductor laminated structure in sequence; A first mask having a predetermined pattern is formed on one insulator layer, and the first mask is used to form the first insulator layer, the first conductor layer, the fifth semiconductor layer, and the first semiconductor layer. A step of sequentially removing a part of the fourth semiconductor layer by etching until a predetermined thickness is obtained, and after removing the first mask, a second mask having a predetermined pattern is formed.
Removing a part of the fourth semiconductor layer and the third semiconductor layer or the fourth semiconductor layer, the third semiconductor layer and the second semiconductor layer by etching using the mask of After removing the second mask and forming a second insulator layer on the entire surface, a third mask having a predetermined pattern is formed on the second insulator layer, and the third mask is formed. By removing the second insulating layer by etching using the second semiconductor layer, a second semiconductor layer is formed on the side surface of the fourth semiconductor layer, the fifth semiconductor layer, the first conductor layer and the first insulating layer. Forming a sidewall made of an insulator layer, removing the third mask, and using the first and second insulator layers as a mask, the fourth semiconductor layer and the third semiconductor layer, or The fourth semiconductor layer, the third semiconductor layer, and After removing a part of the second semiconductor layer by etching, a step of selectively forming a sixth semiconductor layer of a predetermined thickness on the second semiconductor layer, and a step of forming a fourth pattern of a predetermined pattern. Forming a mask, insulating the second semiconductor layer and the first semiconductor layer using the fourth mask, removing the fourth mask, removing the sixth semiconductor layer and the Forming a base electrode made of a second conductor layer having a predetermined pattern on the second insulator layer.

[0028]

[Function] It is not clear what causes the parasitic capacitance other than the external base-collector capacitance in the base-collector capacitance. However, it can be said that the parasitic capacitance occupies most of the capacitance between the base and the collector, especially in the fine element, based on the examination of the high frequency equivalent circuit analysis of the element.

For example, the relative permittivity of SiO ₂ is 1.5 while the relative permittivity of GaAs is 13.1. Therefore, in the conventional bipolar transistor, the insulated G
The lead-out portion of the base electrode formed on the aAs layer is made into Si.
If it is formed on the O ₂ film, it is expected that the parasitic capacitance between the base and the collector associated with this electrode lead portion will be significantly reduced. Moreover, this makes it possible to suppress the base leak current injected into the insulating region immediately below the base electrode lead portion. In this case, as a problem in device manufacturing,
It is conceivable that a step break may occur between the base electrode on the external base layer and the base electrode on the SiO ₂ film formed in the electrode lead portion.
This problem can be solved by suppressing the step difference between the surfaces of the O ₂ film at the connection portion to be smaller than the thickness of the base electrode. The insulating layer formed under the base electrode lead portion is not limited to the SiO ₂ film, but a silicon nitride film, a polyimide film, or the like can be used to obtain the same effect.

Even if the hole injection in the base electrode lead-out portion is prevented, if the insulating regions in contact with the intrinsic base layer and the external base layer are not sufficiently made high in resistance and insulated, hole injection is made from those regions. Occurs, which causes an increase in parasitic capacitance. In general, in a compound semiconductor bipolar transistor, the base layer to be insulated is highly doped, so that the insulating property is likely to be deteriorated by heat treatment during device manufacturing. By removing the base layer in the region other than the intrinsic base layer and the extrinsic base layer, this problem is solved, and the parasitic capacitance can be further reduced.

Similarly, in the conventional bipolar transistor, the emitter lead portion formed on the insulating region is also a factor that increases the parasitic components of the base-emitter capacitance and the base-collector capacitance. Therefore, it is desirable to remove this emitter lead portion in order to further reduce the parasitic capacitance.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A and 1B are a plan view of a bipolar transistor according to a first embodiment of the present invention and x-.
It is an x-ray sectional view.

The structure of this bipolar transistor will be clarified by explaining its manufacturing method. 2 to 9 are cross-sectional views of a semiconductor chip in the order of steps for explaining a method for manufacturing a bipolar transistor according to the first embodiment of the present invention.

First, as shown in FIGS. 2 (a) and 2 (b),
500 nm thick on the semi-insulating substrate 1 made of GaAs,
N-GaAs layer 2 (collector contact layer) having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ , a thickness of 500 nm, and an impurity concentration of 5 ×
10 ¹⁶ cm ⁻³ n-GaAs layer 3 (collector layer), p-GaAs having a thickness of 80 nm and an impurity concentration of 4 × 10 ¹⁹ cm ⁻³
Layer 4 (base layer), undoped GaAs with a thickness of 10 nm
Layer 5 (spacer layer), thickness 150 nm, impurity concentration 3 ×
10 ¹⁷ cm ⁻³ n-Al _0.25 Ga _0.75 As layer 6 (emitter layer), thickness 50 nm, impurity concentration 3 × 10 ¹⁷ cm ⁻³
To 6 × 10 ¹⁸ cm ⁻³ n-Al _x Ga
_1-x As layer (x: 0.25 → 0) 7 (first graded layer), thickness 60 nm, impurity concentration 6 × 10 ¹⁸ cm ⁻³ n-GaAs layer 8, thickness 50 nm, impurity concentration 6 x 1
N-I varied from 0 ¹⁸ cm ^-3 to 2 × 10 ¹⁹ cm ^-3
n _x Ga _1-x As layer (x: 0 → 0.5) 9 (second graded layer), thickness 50 nm, impurity concentration 2 × 10 ¹⁹ c
The m ⁻³ n-In _0.5 Ga _0.5 As layer 10 (emitter contact layer) is sequentially formed by the MBE method. in this case,
Si is used as the n-type impurity and Be is used as the p-type impurity. Subsequently, the WSi layer 11 having a thickness of 300 nm is formed on the entire surface.
And a SiO ₂ film 12 having a thickness of 200 nm are deposited by a sputtering method and a CVD method, respectively, and then a rectangular region 13 is formed.
Is formed, and the SiO ₂ film 12 and the WSi layer 11 are sequentially removed by reactive ion beam etching using CF ₄ and SF ₆ as etching gases, respectively, using the photoresist film 14 as a mask. Further, by reactive ion beam etching using Cl ₂ as an etching gas, n-In _0.5 Ga _0.5 A
s layer 10, n-In _x Ga _1-x As layer 9, n-GaAs
The layer 8 and the n-Al _x Ga _1-x As layer 7 are sequentially removed, and n-Al _0.25 Ga is similarly removed until the thickness becomes about 50 nm.
Etch the _0.75 As layer 6.

Next, as shown in FIGS. 3A and 3B, after cleaning with an organic solvent to remove the photoresist film 14, a rectangular photoresist film 15 which crosses over the rectangular region 13 is formed. .. Using the photoresist film 15 as a mask, a mixture of phosphoric acid, hydrogen peroxide, and water is used for n-A.
The 1 _0.25 Ga _0.75 As layer 6, the undoped GaAs layer 5 and the p-GaAs layer 4 are removed by etching.

Next, as shown in FIGS. 4A and 4B, after the photoresist film 15 is dissolved in an organic solvent, a SiO ₂ film 16 having a thickness of 200 nm is formed on the entire surface. Then S
By forming a photoresist film 18 having a predetermined opening 17 on the iO ₂ film 16 and removing unnecessary portions of the SiO ₂ film 16 by anisotropic reactive ion beam etching, the SiO ₂ film 12 and the WSi layer are formed. 11, n-In _0.5 G
a _0.5 As layer 10, n-In _x Ga _1-x As layer 9, n-
A side wall made of a SiO ₂ film 16 is formed on a side surface of a rectangular parallelepiped made of the GaAs layer 8 and the n-Al _x Ga _1-x As layer 7.

Next, as shown in FIGS. 5A and 5B, after cleaning with an organic solvent to remove the photoresist film 18, the SiO ₂ films 12 and 16 are used as masks to remove phosphoric acid,
N-Al _0.25 Ga with a mixture of hydrogen peroxide and water
_{The 0.75} As layer 6 and the undoped GaAs layer 5 are removed by etching to expose the surface of the p-GaAs layer 4. At this time, n-A having a thickness of about 50 nm is formed under the SiO ₂ film 16.
A protective layer made of l _0.25 Ga _0.75 As layer 6 is formed.
Then, by a molecular beam epitaxy method using trimethyl gallium (Ga (CH ₃ ) ₃ hereafter referred to as TMG) and solid arsenic as a growth raw material, the SiO ₂ films 12 and 16 are used as masks on the p-GaAs layer 4. p-GaAs layer 1
9 is selectively formed. A p-GaAs layer 1 having an impurity concentration of 4 × 10 ²⁰ cm ⁻³ under the conditions of a growth temperature of 450 ° C., a TMG flow rate of 1 cc / min, and an As ₄ partial pressure of 5 × 10 ⁻⁶ Torr.
9 is formed to a thickness of about 260 nm so that the surface of the p-GaAs layer 19 substantially coincides with the surface of the SiO ₂ film 16 in the outer peripheral portion of the rectangular region 17 in contact with the SiO ₂ film 16.

Next, as shown in FIGS. 6A and 6B, a photoresist film is formed to cover the rectangular region 20 forming the bipolar transistor, and the photoresist film is used as a mask to remove the rectangular region 20 and other portions. Acceleration voltage 14
H ⁺ is implanted under the conditions of 5 keV and a dose amount of 3 × 10 ¹⁵ cm ⁻² to form the insulating region 21. Subsequently, after removing the photoresist film described above, H ⁺ is injected under the conditions of an acceleration voltage of 100 keV and a dose amount of 5 × 10 ¹² cm ⁻² , thereby reducing the parasitic capacitance between the external base and the collector.

Next, as shown in FIGS. 7A and 7B, U
Photoresist film having V-shaped openings 22 (not shown)
After forming the film, Ti50nm, Pt50nm, Au15
A Ti / Pt / Au layer of 0 nm is formed by vapor deposition from above, and liftoff is performed to form the base electrode 23. Subsequently, a photoresist film (not shown) having a predetermined pattern 24 for collector opening is formed, and using this as a mask, the SiO ₂ film 16 is formed by buffered hydrofluoric acid, and the mixed solution of phosphoric acid, hydrogen peroxide and water is formed. n-Ga
By sequentially removing the As layer 3 by etching, n
-Exposing the surface of the GaAs layer 2. Furthermore, n from above
-AuGe / Ni which is the ohmic metal of the GaAs layer 2
/ Au layer is vapor-deposited, lift-off is performed, and collector electrode 2
5 is formed.

Next, as shown in FIGS. 8A and 8B, after a SiO ₂ film 26 is formed on the entire surface and flattened, a photoresist film having a rectangular opening 27 for taking out the emitter electrode ( (Not shown). Using this photoresist film as a mask, the SiO ₂ film 26 and the SiO ₂ film 12 are sequentially removed by reactive ion beam etching using CF ₄ as an etching gas to remove WSi.
The surface of layer 11 is exposed. Then, Ti / Pt /
After depositing the Au layer by the sputtering method, a photoresist film 29 covering the rectangular region 28 for forming the emitter electrode is formed. Using the photoresist film 29 as a mask, an unnecessary portion of the Ti / Pt / Au layer is removed by an ion milling method to form an emitter electrode 30.

Next, as shown in FIG. 9, the photoresist film 29 is removed, and a SiO ₂ film 31 having a thickness of 500 nm is formed on the entire surface. Subsequently, contact holes 32b, 32c and 32e are provided at predetermined locations on the SiO ₂ film 31. An electrode pad (not shown) connected to the base electrode 23, the collector electrode 25 and the emitter electrode 30 through the contact holes 32b, 32c and 32e, respectively, is S.
Formed on the iO ₂ film 31, a compound semiconductor bipolar transistor as shown in FIGS. 1A and 1B is completed. In FIG. 1A, the portion covered only with the SiO ₂ films 31 and 26 is drawn by a solid line.

When the high frequency equivalent circuit analysis of the bipolar transistor of the present invention thus obtained was conducted, the base-collector parasitic capacitance was about 1/3 and the base-emitter parasitic capacitance was about 1/3 as compared with the conventional structure. It has been confirmed that the present invention has a remarkable effect in reducing the parasitic capacitance of the element and improving the high speed / high frequency characteristics.

In the first embodiment described above, p-G
The case where the aAs layer 19 is formed as the base contact layer has been described. In the second embodiment of the present invention, p-G
A case where the aAs layer 19 is formed over the entire external base region will be described.

In the second embodiment, n in FIG.
-Al _0.25 Ga _0.75 As layer 6, undoped GaAs layer 5
And p-GaAs layer 4 is removed by etching, and n-
After exposing the GaAs layer 3, the SiO ₂ films 12 and 16 are formed.
With a thickness of approximately 340 nm on the n-GaAs layer 3 as a mask
P-GaAs layer 19 is selectively formed, and the SiO ₂ film 1 is formed.
6 in the outer peripheral portion of the rectangular region 17 that is in contact with p-GaA
The surface of the s layer 19 is made to substantially coincide with the surface of the SiO ₂ film 16. The subsequent steps may be performed according to the first embodiment. As a result, a compound semiconductor bipolar transistor as shown in FIGS. 9A and 9B is obtained, and the same effect as that of the first embodiment is obtained.

Next, a third embodiment of the present invention will be described.

10 (a) and 10 (b) are a plan view and x of a bipolar transistor according to the third embodiment of the present invention.
FIG. 6 is a cross-sectional view taken along line x.

The structure of this bipolar transistor will be clarified by explaining its manufacturing method.

First, as shown in FIGS. 11 (a) and 11 (b),
Similar to the first embodiment, a semi-insulating substrate 1 made of GaAs
An n-GaAs layer 2 (collector contact layer) having a thickness of 500 nm and an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ , a thickness of 50
N-GaAs layer 3 (collector layer) having a thickness of 0 nm and an impurity concentration of 5 × 10 ¹⁶ cm ⁻³ has a thickness of 80 nm and an impurity concentration of 8 × 10
¹⁹ cm ^-3 p-GaAs layer 4 (base layer), thickness 150
nm, impurity concentration 3 × 10 ¹⁷ cm ⁻³ n-Al _0.25 Ga
_0.75 As layer 6 (emitter layer), thickness of 50 nm, n-Al _x Ga _1-x As layer (x: 0. 0.) with the impurity concentration changed from 3 × 10 ¹⁷ cm ⁻³ to 6 × 10 ¹⁸ cm ⁻³ . 25 → 0) 7
(First graded layer), thickness 60 nm, n-GaAs layer 8 with impurity concentration 6 × 10 ¹⁸ cm ⁻³ , thickness 50 nm,
_{N-In x Ga 1-x} As layer with varying impurity concentration of 6 × 10 ¹⁸ cm ^-3 to ^{2 × 10 19 cm -3 (x} : 0 → 0.
5) 9 (second graded layer), thickness of 50 nm, impurity concentration of 2 × 10 ¹⁹ cm ⁻³ n-In _0.5 Ga _0.5 As
The layer 10 (emitter contact layer) is sequentially formed by MOCVD. In this case, the n-type impurity is Si, p
C is used as the type impurity. Then, the thickness of 30
0 nm WSi layer 11 and 200 nm thick SiO ₂
After depositing the film 12 by the sputtering method and the CVD method, respectively, a photoresist film 14 covering the rectangular region 13 is formed, and using this photoresist film 14 as a mask, SiO ₂
The film 12 and the WSi layer 11 are provided with CV ₄ and SF, respectively.
₆ is sequentially removed by reactive ion beam etching using an etching gas.

Next, as shown in FIGS. 12 (a) and 12 (b),
After removing the photoresist film 14, a photoresist film (not shown) covering the rectangular region 20 forming the bipolar transistor is formed, and the accelerating voltage 20 is applied to other portions except the rectangular region 20 by using this photoresist film as a mask.
0 keV, dose 3 × 10 ¹⁵ cm ^-2 and acceleration voltage 5
H ⁺ is double-implanted under the conditions of ⁰ keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² to form the insulating region 21. The main purpose is to insulate the collector contact layer in the first implantation, and to insulate the base layer in the second implantation. continue,
After removing the photoresist film described above, the n-In _0.5 Ga _0.5 As layer 10 and the n-In _x Ga layer 10 are mixed with phosphoric acid, hydrogen peroxide and water using the SiO ₂ film 12 as a mask.
_1-x As layer 9, n-GaAs layer 8, n-Al _x Ga _1-x
The As layer 7 and the n-Al _0.25 Ga _0.75 As layer 6 are sequentially etched and removed to expose the surface of the p-GaAs layer 4. Furthermore, the acceleration voltage is 70 keV and the dose is 5 × 10 ^12.
H ⁺ is injected under the condition of cm ⁻² , which allows the external base
Reduces parasitic capacitance between collectors.

Next, as shown in FIGS. 13 (a) and 13 (b),
After forming a 100 nm thick SiO ₂ film 16 on the entire surface,
The SiO ₂ film 16 (not shown) photoresist film having a predetermined opening 17 is formed on the formation, which the SiO ₂ film 16 and 12 are removed by etching with buffered hydrofluoric acid as a mask. Then, after removing the photoresist film and forming a new photoresist film (not shown) having a rectangular opening 22, a 250 nm-thick Ti / Pt /
The Au layer 23b is formed by vapor deposition from above, and liftoff is performed to form the base electrode 23 in a self-aligned manner. Subsequent steps may be performed according to the first embodiment.

As a result, a compound semiconductor bipolar transistor as shown in FIGS.
The same effects as those of the first and second embodiments can be obtained.

Although the base layer is made of p-GaAs in the above-mentioned first to third embodiments, the present invention is not limited to this. For example, p-AlGa is used.
The same effect can be obtained when the graded base structure is formed by gradually changing the Al composition of the base layer made of As, or when the base layer contains In and p-InGaAs or the like is used.

[0054]

As described above, according to the present invention, f _T and f _max can be improved by significantly reducing the parasitic capacitance between the base and the collector and between the base and the emitter. As a result, there is an effect that a bipolar transistor of a compound semiconductor having excellent high speed and high frequency characteristics can be realized.

[Brief description of drawings]

FIG. 1 is a first bipolar transistor according to the present invention.
FIG. 1 is a plan view used to explain the embodiment of FIG.
It is (a)) and sectional drawing (FIG.1 (b)).

2A and 2B are a plan view (FIG. 2A) and a sectional view (FIG. 2B) used for explaining a first embodiment of a method for manufacturing a bipolar transistor according to the present invention.

3A and 3B are a plan view (FIG. 3A) and a sectional view (FIG. 3B) used for explaining a first embodiment of a method of manufacturing a bipolar transistor according to the present invention.

FIG. 4 is a plan view (FIG. 4A) and a sectional view (FIG. 4B) used for explaining a first embodiment of a method for manufacturing a bipolar transistor according to the present invention.

5A and 5B are a plan view (FIG. 5A) and a cross-sectional view (FIG. 5B) used for explaining a first embodiment of a method for manufacturing a bipolar transistor according to the present invention.

6A and 6B are a plan view (FIG. 6A) and a sectional view (FIG. 6B) used for explaining a first embodiment of a method for manufacturing a bipolar transistor according to the present invention.

7A and 7B are a plan view (FIG. 7A) and a sectional view (FIG. 7B) used for explaining a first embodiment of a method for manufacturing a bipolar transistor according to the present invention.

8A and 8B are a plan view (FIG. 8A) and a sectional view (FIG. 8B) used for explaining a first embodiment of a method for manufacturing a bipolar transistor according to the present invention.

9A and 9B are a plan view (FIG. 9A) and a cross-sectional view (FIG. 9B) used for explaining a second embodiment of the bipolar transistor manufacturing method according to the invention.

10A and 10B are a plan view (FIG. 10A) and a sectional view (FIG. 10B) used for explaining a third embodiment of the method for manufacturing a bipolar transistor according to the present invention.

11A and 11B are a plan view (FIG. 11A) and a sectional view (FIG. 11B) used for explaining a third embodiment of the method for manufacturing a bipolar transistor according to the present invention.

12A and 12B are a plan view (FIG. 12A) and a sectional view (FIG. 12B) used for explaining a third embodiment of the method for manufacturing a bipolar transistor according to the present invention.

13A and 13B are a plan view (FIG. 13A) and a sectional view (FIG. 13B) used for explaining a third embodiment of the method for manufacturing a bipolar transistor according to the present invention.

14A and 14B are a plan view (FIG. 14A) and a cross-sectional view (FIG. 14B) used for explaining a conventional method for manufacturing a bipolar transistor.

15A and 15B are a plan view (FIG. 15A) and a cross-sectional view (FIG. 15B) used for explaining a conventional method for manufacturing a bipolar transistor.

16A and 16B are a plan view (FIG. 16A) and a cross-sectional view (FIG. 16B) used for explaining a conventional method for manufacturing a bipolar transistor.

17A and 17B are a plan view (FIG. 17A) and a cross-sectional view (FIG. 17B) used for explaining a conventional method for manufacturing a bipolar transistor.

[Explanation of symbols]

1 semi-insulating substrate (GaAs) 2,3,8 n-GaAs layer 4,19 p-GaAs layer 5 undoped GaAs layer 6 n-Al _0.25 Ga _0.75 As layer 7 n-Al _x Ga _1-x As layer (x : 0.25 → 0) 9 n-In _x Ga _1-x As layer (x: 0. → 0.5) 10 n-In _0.5 Ga _0.5 As layer 11 WSi layer 12, 16, 26, 26 a, 31 SiO ₂ film 13, 13a, 28 rectangular area 15, 29 photoresist film 17, 22, 24, 27 opening 20 rectangular area 21 insulating area 23, 23a base electrode 23b TiPtAu layer 23c AuMn layer 25 collector electrode 30, 30a emitter electrode 32b, 32c , 32e Contact hole

Claims (6)

[Claims] 1. At least a collector layer on a semi-insulating substrate,
In a bipolar transistor in which a semiconductor laminated structure including a base layer and an emitter layer is formed, an intrinsic base layer is formed and formed in a first region, and an external base layer electrically coupled to the intrinsic base layer is a second region. And the base layer is removed in the third region excluding the first and second regions, and at least a part of the base electrode extracted to the third region is formed on the insulator layer. A bipolar transistor characterized by being formed. 2. At least a collector layer on a semi-insulating substrate,
In a bipolar transistor in which a semiconductor laminated structure including a base layer and an emitter layer is formed, an intrinsic base layer is formed and formed in a first region, and an external base layer electrically coupled to the intrinsic base layer is a second region. The base layer is insulated in the third region excluding the first and second regions, and at least a part of the base electrode extracted to the third region is formed on the insulator layer. A bipolar transistor characterized by being formed. 3. The bipolar transistor according to claim 1, wherein the step difference between the external base layer and the insulator layer at the boundary between the second region and the third region is smaller than the thickness of the base electrode. .. 4. The bipolar transistor according to claim 1 or 2, wherein an emitter layer is formed and arranged inside a fourth region formed by the first region and the second region. 5. A semi-insulating substrate having at least a collector contact layer made of a first semiconductor layer, a collector layer made of a second semiconductor layer, a base layer made of a third semiconductor layer, and a fourth semiconductor layer. Forming a semiconductor laminated structure including an emitter contact layer composed of an emitter layer and a fifth semiconductor layer; forming a first conductor layer and a first insulator layer on the semiconductor laminated structure in sequence; A first mask having a predetermined pattern is formed on one insulator layer, and the first mask is used to form the first insulator layer, the first conductor layer, the fifth semiconductor layer, and the first semiconductor layer. A step of sequentially removing a part of the fourth semiconductor layer to a predetermined thickness by etching, and a step of removing the first mask and then a second pattern having a predetermined pattern.
Forming a mask, and using the second mask, the fourth mask is formed.
Removing a part of the semiconductor layer and the third semiconductor layer, or the fourth semiconductor layer, the third semiconductor layer and the second semiconductor layer by etching, and removing the second mask. Then, a second insulator layer is formed on the entire surface, a third mask having a predetermined pattern is formed on the second insulator layer, and the second insulator is formed using the third mask. By removing the layer by etching,
Forming a sidewall made of a second insulator layer on a side surface of the fourth semiconductor layer, the fifth semiconductor layer, the first conductor layer, and the first insulator layer; The mask is removed, the fourth semiconductor layer or a part of the fourth semiconductor layer and the third semiconductor layer is removed by etching using the first and second insulator layers as a mask, and then, A step of selectively forming a sixth semiconductor layer having a predetermined thickness on the third semiconductor layer; and forming a fourth mask having a predetermined pattern, and using the fourth mask, the second mask is formed. Insulating the semiconductor layer and the first semiconductor layer, removing the fourth mask, and forming a second conductor layer in a predetermined pattern on the sixth semiconductor layer and the second insulator layer And forming a base electrode made of Method of manufacturing over La transistor. 6. A semi-insulating substrate having at least a collector contact layer made of a first semiconductor layer, a collector layer made of a second semiconductor layer, a base layer made of a third semiconductor layer, and a fourth semiconductor layer. Forming a semiconductor laminated structure including an emitter contact layer composed of an emitter layer and a fifth semiconductor layer; forming a first conductor layer and a first insulator layer on the semiconductor laminated structure in sequence; A first mask having a predetermined pattern is formed on one insulator layer, and the first mask is used to form the first insulator layer, the first conductor layer, the fifth semiconductor layer, and the first semiconductor layer. A step of sequentially removing a part of the fourth semiconductor layer to a predetermined thickness by etching, and a step of removing the first mask and then a second pattern having a predetermined pattern.
Forming a mask, and using the second mask, the fourth mask is formed.
Removing a part of the semiconductor layer and the third semiconductor layer, or the fourth semiconductor layer, the third semiconductor layer and the second semiconductor layer by etching, and removing the second mask. Then, a second insulator layer is formed on the entire surface, a third mask having a predetermined pattern is formed on the second insulator layer, and the second insulator is formed using the third mask. By removing the layer by etching,
Forming a sidewall made of a second insulator layer on a side surface of the fourth semiconductor layer, the fifth semiconductor layer, the first conductor layer, and the first insulator layer; The mask is removed, and the fourth semiconductor layer and the third insulating layer are used as masks.
Part of the fourth semiconductor layer, the fourth semiconductor layer, the third semiconductor layer, or the second semiconductor layer is removed by etching, and then a sixth layer having a predetermined thickness is formed on the second semiconductor layer. Selectively forming the semiconductor layer, and a step of forming a fourth mask having a predetermined pattern and insulating the second semiconductor layer and the first semiconductor layer using the fourth mask. And removing the fourth mask to form a base electrode composed of a second conductor layer having a predetermined pattern on the sixth semiconductor layer and the second insulator layer. And method for manufacturing bipolar transistor.