JPH06209077A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide such a semiconductor device that a bipolar transistor and HEMT can be formed on the same substrate at a high yield and low cost without making any selective growth and its manufacturing method. CONSTITUTION:In this device in which a heterojunction bipolar transistor and heterojunction field-effect transistor are constituted on the same substrate, the bipolar transistor is constituted by successively piling up emitter layers 2 and 3a, a base layer 4a, a non-doped collector layer 5a, and a sub-collector layer having a band gap larger than that of the layer 5a on a substrate 1. The heterojunction field-effect transistor is constituted by successively piling up a channel layer 5b composed of the same material as that of the layer 5a and electron supplying layer 6b composed of the same material as that of the layer 6a on the substrate 1, with the layers 5b and 6a being separated from the layers 5a and 6a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, it can apply a heterojunction bipolar transistor (HBT) and a heterojunction field effect transistor (HEMT) to a compound semiconductor integrated circuit or the like. In particular, the present invention relates to a semiconductor device and a manufacturing method thereof which can be formed by hybridizing and integrating HBT and HEMT on the same substrate at a low cost with good yield without using selective growth.

Recently, HBT and HE using compound semiconductors
Since both MTs have excellent high-frequency characteristics and high-speed characteristics, they are expected to be applied to ultra-high-speed digital communication, microwave, millimeter wave band communication and the like. HBT and HEMT each have some advantages and disadvantages. For example, when configuring a low noise amplifier, NF is very small in HEMT and very large in HBT. Is more advantageous, and in phase noise, HE
Very large in MT and very small in HBT,
When configuring a VCO or the like, it is advantageous to use HBT. For this reason, research and development of a hybrid integrated circuit in which HBT and HEMT are hybrid-integrated are actively conducted in order to make up for each other's drawbacks and utilize their advantages.

[0003]

2. Description of the Related Art FIG. 4 is a sectional view showing the structure of a conventional semiconductor device. The illustrated example is applied to a hybrid integrated circuit of HBT and HEMT. As shown in FIG. 4, first, on the semi-insulating GaAs substrate 31, the n ⁺ -GaAs collector layer 32, the n ^-- GaAs base layer 33, the p ⁺ -GaAs base cap layer 34, and the n-Al are formed by the selective epitaxial growth method.
A GaAs emitter layer 35 and an n ⁺ -GaAs emitter cap layer 36 are sequentially formed, an emitter electrode 37 is formed on the n ⁺ -GaAs emitter cap layer 36, and a base electrode 38 is formed on the p ⁺ -GaAs base cap layer 34. , N ⁺ -G
The HBT is formed by forming the collector electrode 39 on the aAs collector layer 32. At this time, each layer to be stacked on the HEMT side is removed by etching. next,
The non-doped GaAs channel layer 41, n ⁺ -A is formed on the other portion of the GaAs substrate 31 by the selective epitaxial growth method.
lGaAs electron supply layer 42 and n ⁺ -GaAs cap layer
43 are sequentially formed, and source / drain electrodes 44, which are ohmic electrodes, are formed on the n ⁺ -GaAs cap layer 43.
^A HEMT is formed by forming a gate electrode 45, which is a Schottky electrode, on the ⁺ -AlGaAs electron supply layer 42. At this time, the formed HBT is covered with a mask for protection.

[0004]

As described above, according to the conventional semiconductor device and the manufacturing method thereof, the HBT and the HEMT are used.
Are separately formed by the selective epitaxial growth method. In this selective growth method, the formed HBT must be protected by a mask when the HEMT is formed. This mask is used for film formation and etching during the HEMT formation. Is not easily protected against damage to the element side, or if it is formed thick enough to prevent damage, the distance between the HBT and HEMT becomes extremely large, and it is not suitable for mold reduction. There is a problem that the yield is deteriorated because the variation of the element tends to be large. As described above, the selective growth method has various problems, and it has not been established as a technology.

Further, since the HBT and the HEMT were separately formed by the selective growth method, each layer and each electrode had to be formed independently, resulting in an increase in the number of steps and an increase in manufacturing cost. There was a problem. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device and a manufacturing method thereof in which the HBT and the HEMT can be formed on the same substrate at a good yield without using selective growth and at a low cost.

[0006]

To achieve the above object, a semiconductor device according to the present invention is a semiconductor device in which a heterojunction bipolar transistor and a heterojunction field effect transistor are formed on the same substrate.
A base layer, a non-doped collector layer, and a subcollector layer having a bandgap larger than that of the collector layer are sequentially stacked to form a heterojunction bipolar transistor,
A heterojunction electric field is formed by sequentially stacking on the substrate a channel layer made of the same material as the collector layer and spaced apart from the collector layer, and an electron supply layer made of the same material as the subcollector layer spaced apart from the collector layer. The effect transistor is configured.

In order to achieve the above object, the method of manufacturing a semiconductor device according to the present invention has a non-doped collector layer which also functions as an emitter layer, a base layer, and a channel layer on a substrate, has a bandgap larger than that of the collector layer, and has an electron A step of sequentially forming a subcollector layer also serving as a supply layer and a cap layer, a step of etching the cap layer into a predetermined shape to expose the subcollector layer, and a step of also serving as the electron supply layer. The collector layer, which also serves as the subcollector layer and the channel layer, is etched into a predetermined shape to form a subcollector layer, an electron supply layer separated from the subcollector layer is formed, and a collector layer is formed. Forming a channel layer separated from the collector layer,
Further, it includes a step of exposing the base layer and a step of etching the base layer and the emitter layer in a predetermined shape.

In the present invention, it is preferable to form the collector electrode and the source / drain electrodes on the cap layer at the same time. In this case, the number of steps is larger than that in the conventional case where the collector electrode and the source / drain electrodes are formed separately. Therefore, the manufacturing cost can be reduced. In the present invention, it is preferable to form a gate electrode on the electron supply layer and at the same time form a base electrode on the base layer. In this case, it is preferable to form a conventional gate electrode and base electrode separately. Also, since the number of steps can be reduced, the manufacturing cost can be reduced.

[0009]

In the present invention, as shown in FIGS.
A non-doped layer is used for the collector layer 5a of the BT, the non-doped layer is commonly used for the channel layer 5b of the HEMT, and the sub-collector layer 6a of the HBT is made of a material having a bandgap larger than that of the collector layer 5a. A layer having a band gap larger than that of the collector layer 5a is HEM
Since the T electron supply layer 6b is used in common, the HBT and HEMT can be simultaneously formed on the same substrate 1 without using the selective growth technique. Moreover, since a normal semiconductor process technology can be used instead of the selective growth technology, the number of steps can be reduced and the cost can be reduced as compared with the case where the conventional selective growth technology is separately formed. Since it is not necessary to form a difficult mask unlike the growth technique, it can be formed with high yield.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. The illustrated example is applied to a hybrid integrated circuit of HBT and HEMT, in which a collector-up type HBT is formed in a region A, and a HEMT is formed in the region B on the same substrate. First, the HBT side of the area A will be described. In FIG. 1, 1 is a substrate of semi-insulating GaAs or the like, 2 is a cap layer of n ⁺ -GaAs or the like formed on the substrate 1 and also serving as an emitter cap, and 3a is formed on the cap layer 2. N-AlGaAs is an emitter layer, and 4a is p ⁺ -G formed on the emitter layer 3a.
It is a base layer such as aAs. Next, 5a is the base layer 4
a collector layer such as i-GaAs formed on a,
Reference numeral 6a denotes a sub-collector layer formed on the collector layer 5a, such as n ⁺ -AlGaAs having a larger band gap than the collector layer 5a, and 7a denotes a collector cap formed on the sub-collector layer 6a, such as n ⁺ -GaAs. It is a layer. Next, 8 is a collector electrode of AuGe / Au or the like formed on the collector cap layer 7a, 9 is a base electrode of Ti / Pt / Au or the like formed on the base layer 4a, and 10 is a cap layer 2 AuGe / A formed on top
It is an emitter electrode of u or the like, and an HBT is composed of the above respective parts. Next, the HEMT side of the region B will be described. Figure 1
3b is an n-AlGaAs layer formed of the same material as the emitter layer 3a formed on the cap layer 2,
4b is ap ⁺ -GaAs layer formed of the same material as the base layer 4a formed on the n-AlGaAs layer 3b, and 5b
P ⁺ -GaAs is formed on p ⁺ -GaAs layer 4b
An i-GaAs channel layer made of the same material as the collector layer 5a having a bandgap larger than that of the layer 4b.
Is a two-dimensional electron gas formed on the channel layer 5b, 6b is an n ⁺ -AlGaAs electron supply layer made of the same material as the subcollector layer 6a formed on the channel layer 5b, and 7b is an electron supply layer. This is a cap layer made of the same material as the collector cap layer 7a formed on 6b, such as n ⁺ -GaAs. 11 is a gate electrode of Ti / Pt / Au or the like formed on the electron supply layer 6b, and 12
Is a source / drain electrode of AuGe / Au or the like formed on the cap layer 7b, and the HEMT is composed of the above respective parts. Reference numeral 13 is an element isolation region formed from the cap layer 2 for isolating the HBT and the HEMT to the substrate 1.

2 and 3 are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2, 3
1, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions,
Reference numeral 3 denotes HBT and HEMT regions A and B on the cap layer 2.
N is an emitter layer of n-AlGaAs or the like formed by the above process, 4 is a base layer formed on the emitter layer 3, and 5 is a channel layer such as i-GaAs formed on the base layer 4. A collector layer 6 also serves as n ⁺ -AlGaAs formed on the collector layer 5 also serving as a channel layer.
Is a subcollector layer also serving as an electron supply layer, and 7 is an n ⁺ film formed on the subcollector layer 6 also serving as an electron supply layer.
-A cap layer such as GaAs.

Next, a method of manufacturing the semiconductor device
explain. First, as shown in FIG. 2A, MOCVD is performed.
Si dopant on the semi-insulating GaAs substrate 1 by the method
Impurity concentration 5 × 10¹⁸cm^-3With a film thickness of about 5000Å
⁺-GaAs emitter cap layer 2, no Si dopant
Pure substance concentration 5 × 10¹⁷cm^-3With film thickness of 1500 Å
Al_XGa_1-XAs (X = 0.3) emitter layer 3, car
Bon (C) dopant impurity concentration 4 × 10¹⁹cm^-3Film thickness
And p of about 700Å ⁺-GaAs base layer 4, film thickness 40
A collector that also serves as an i-GaAs channel layer of about 00Å
Layer 5, Si dopant impurity concentration 2 × 10¹⁸cm^-3With membrane
N with a thickness of 250Å⁺-Al_XGa_1-XAs electron supply layer
The sub-collector layer 6 also serving as the Si and the dopant concentration of the Si dopant
5 × 10¹⁸cm^-3With a film thickness of 500Å⁺-GaA
The s cap layer 7 is sequentially formed.

Next, as shown in FIG. 2B, AuGe / Au (3) is formed on the cap layer 7 by the vapor deposition method and the RIE method.
(00Å / 300Å) collector electrode 8 is formed, and at the same time, AuGe / Au (300Å / 30) is formed on the cap layer 7.
0 Å) Source / drain electrodes 12 are formed. Then, heat treatment is performed at about 450 ° C. to obtain ohmic contact.

Next, as shown in FIG. 2C, the cap layer 7 is etched into a predetermined shape by the RIE method or the like using the collector electrode 8 and the source / drain electrode 12 as a mask to form a collector cap layer 7a. Together with this, the source / drain cap layer 7b is formed. At this time, the subcollector layer 6 which also serves as the electron supply layer is exposed. Next, as shown in FIG. 2D, Ti / Pt / Au (10) is formed on the sub-collector layer 6 which also serves as the electron supply layer between the source / drain cap layers 7b by the vapor deposition method and the RIE method.
00Å / 900Å / 3000Å) The gate electrode 11 is formed.

Next, as shown in FIG. 3A, the subcollector layer 6 also serving as the electron supply layer and the collector layer 5 also serving as the channel layer are etched into a predetermined shape by RIE or the like to form a subcollector layer. 6a is formed, an electron supply layer 6b is formed apart from the sub-collector layer 6a, a collector layer 5a is formed, and a channel layer 5b is formed apart from the collector layer 5a. At this time, the base layer 4
Is exposed.

Next, as shown in FIG. 3 (b), Ti / Pt / Au (1000Å / 90, which becomes a non-naloy ohmic contact on the base layer 4 by the vapor deposition method and the RIE method or the like.
0Å / 3000Å) The base electrode 9 is formed. Next, as shown in FIG. 3C, the base layer 4 and the emitter layer 3 are etched by the RIE method or the like to form a base layer 4a and a p ⁺ -GaAs layer 4b separated from the base layer 4a is formed. The emitter layer 3a and the n-AlGaAs layer 3b separated from the emitter layer 3a.
To form. At this time, the cap layer 2 is exposed. Then, AuG is formed on the cap layer 2 by the vapor deposition method and the RIE method.
After forming the e / Au (300Å / 3000Å) emitter electrode 10, 450 ℃ to obtain good contact resistance
A heat treatment is performed to some extent, and thereafter, an element isolation region 13 is formed from the cap layer 2 to the substrate 1 for element isolation between the HBT and the HEMT, whereby a semiconductor device as shown in FIG. 1 can be obtained.

As described above, in this embodiment, a non-doped layer is used for the collector layer 5a of the HBT, the non-doped layer is used for the channel layer 5b of the HEMT, and the sub-collector layer 6a of the HBT is more common than the collector layer 5a. This collector layer 5 is formed by using a layer made of a material having a large band gap.
Since a layer having a bandgap larger than that of a is used in common for the electron supply layer 6b of the HEMT, the HBT and the HEMT can be simultaneously formed on the same substrate 1 without using the selective growth technique. Moreover, since a normal semiconductor process technology can be used instead of the selective growth technology, the number of steps can be reduced and the cost can be reduced as compared with the case where the conventional selective growth technology is separately formed. Since it is not necessary to form a difficult mask unlike the growth technique, the mask can be formed with high yield.

Further, since the collector electrode 8 and the source / drain electrode 12 are simultaneously formed on the cap layer 7, the number of steps can be reduced as compared with the conventional case where the collector electrode and the source / drain electrode are separately formed. The manufacturing cost can be reduced. In the above embodiment,
Although the case where the gate electrode 11 and the base electrode 9 are separately formed has been described, the present invention is not limited to this. The gate electrode 11 is formed on the electron supply layer 6b, and at the same time, the base electrode 4a is formed on the base layer 4a. The electrode 9 may be formed. In this case, the number of steps can be reduced as compared with the conventional case where the gate electrode and the base electrode are separately formed, so that the manufacturing cost can be reduced.

[0019]

According to the present invention, HBT and HEM can be produced on the same substrate with good yield without using selective growth and at low cost.
There is an effect that T can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

1 substrate 2 cap layer 3, 3a emitter layer 3b n-AlGaAs layer 4, 4a base layer 4b p ⁺ -GaAs layer 5, 5a collector layer 5b channel layer 5c two-dimensional electron gas 6, 6a subcollector layer 6b electron supply layer 7a Collector cap layer 7, 7b Cap layer 8 Collector electrode 9 Base electrode 10 Emitter electrode 11 Gate electrode 12 Source / drain electrode 13 Element isolation region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 29/73 21/338 29/812 27/095 8427-4M H01L 29/72 7376-4M 29 / 80 H 7376-4ME

Claims (4)

[Claims] 1. In a semiconductor device in which a heterojunction bipolar transistor and a heterojunction field effect transistor are formed on the same substrate, an emitter layer (2, 3a), a base layer (4a) and a non-doped collector are provided on a substrate (1). A heterojunction bipolar transistor is formed by sequentially stacking a layer (5a) and a subcollector layer (6a) having a bandgap larger than that of the collector layer (5a), and forming a heterojunction bipolar transistor on the substrate (1) with the collector layer (5a). A channel layer (5b) made of the same material as the collector layer (5a) and an electron supply layer (6b) made of the same material as the subcollector layer (6a) are formed apart from the channel layer (5b) and the subcollector layer (6a). A semiconductor device comprising heterojunction field effect transistors which are sequentially stacked. 2. An emitter layer (2, 3) on a substrate (1),
A base layer (4), a non-doped collector layer (5) also serving as a channel layer, a sub-collector layer (6) having a band gap larger than that of the collector layer (5) and also serving as an electron supply layer, and a cap layer (7). ) Are sequentially formed, then the cap layer (7) is etched into a predetermined shape to expose the sub-collector layer (6), and then the sub-collector layer (also serving as the electron supply layer) is formed. 6) and the collector layer (5) also serving as a channel layer are etched in a predetermined shape to form a subcollector layer (6a), and an electron supply layer (6b) separated from the subcollector layer (6a) is formed. Forming and forming a collector layer (5a), forming a channel layer (5b) separated from the collector layer (5a), and further exposing the base layer (4); The method of manufacturing a semiconductor device which comprises a step of etching over scan layer (4) and said emitter layer (3) in a predetermined shape. 3. The method for manufacturing a semiconductor device according to claim 2, wherein a collector electrode (8) and a source / drain electrode (12) are simultaneously formed on the cap layer (7). 4. The gate electrode (11) is formed on the electron supply layer (6b), and at the same time, the base electrode (9) is formed on the base layer (4). A method for manufacturing a semiconductor device as described above.