JPS59161878A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to stabilize a Schottky junction by a method wherein a gate electrode wiring of the double layer structure of Si and high melting point metal is formed, which is thereafter annealed, thus changing the Si film into a high melting point silicide film. CONSTITUTION:A region serving later as an operating layer is formed on a compound semiconductor substrate 51, an Si film 53 is adhered thereon, and further an Mo film is formed. Afterwards, a gate electrode 54 is formed by etching only the Mo film with a patterned resist as a mask. Next, with the electrode 54 and the resist pattern 53 as a mask, Si ions are implanted to the substrate 51 through the film 53, thus forming a high concentration impurity implanted region 56. Then, after depositing an Si oxide film 57 over the entire surface, the implanted impurity is activated by annealing, and at the the same time the Si film under the electrode 54 is changed into the silicide layer 58. This manufacture makes a high melting point metallic silicide film existent in contact with the surface of the region 52, and accordingly the Schottky junction characteristic remains stable even after annealing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a compound semiconductor device including a compound semiconductor field effect transistor. Contains information on how to send money.

Compound semiconductors, such as gallium arsenide, are
Since it has an electron mobility that is 5 to 6 times higher, it is possible for transistors and integrated circuits to be cracked, which are capable of more efficient operation than when silicon is used. When using K1 cigallium, it is possible to form a stable insulating layer on the same crystal, so it is possible to form a Schottky gate electrophoresis infant transistor (hereinafter mw s F
(referred to as kJT) is currently being tested.

Figure 1 is a mata-style cross-sectional view of 1vlJ4sFnT69,
1 is a half loquat tR substrate, 2 is an active layer, 3 is a Schottky gate, and 4 is a source or drain 11! As is well known, the current flowing between the drain and source is
The voltage applied to the gate electrode is modulated. In actual transistors, as a result of the presence of surface depletion nodes as shown in 5, the parasitic series resistance between the source and gate and between the gate and drain increases, resulting in deterioration of the electrical characteristics of the transistor, such as a decrease in mutual conductance, etc. occurs. Therefore, at present, this series resistance (hereinafter f(+s
Transistor structures or manufacturing methods that can reduce the Figure 2 shows #lC in which the source and drain electrodes are formed close to the gate electrode.
The Matata type 11TO FET aims to reduce Rs!
I figure is out. 1 to 4 are installed in the same parts as in Figure 1. The structure is realized as a short-circuit structure, and the gate electrode material is used as a whole resist mask to form a distorted shape by etching, and the over-erating layer is removed, and the source/drain electrode metal material is vapor-layered as it is. The distance between the gate electrode and the source/drain electrode was shortened by taking advantage of the conflict between the source and V in'kL extremes at the edge of the resist due to lift-off (φ). By using this noise area reduction, it is possible to reduce Rs and improve the characteristics of the FET.However, it is difficult to control the amount of overetching of the gate electrode, and There is a limit to etch It, and currently the distance between the gate electrode and the source/drain electrode is about 0.4 microns, and although the S value is reduced compared to the example shown in Figure 1, it is possible to reduce the pattern thickness of elements in the future. This short-range pole-to-pole structure is not satisfactory for FMTlf due to the fact that ns reduction cannot be obtained, etc.
It's not a G-built one.

In order to reduce S, it is necessary to selectively add impurities that exhibit the same conductivity as the active layer only in the regions that will become the source and drain regions.
! It is a good idea to press-fit + at once and reduce the 7-t resistance value in the source area. As for the engineer 'E'f', who was envied by his failure to implant ions into the source/drain area, it is known that there are 2 hozuke's from the envoys. Figure 3 shows a schematic cross-sectional view of PET manufactured by using a heat-resistant gate material and injecting impurities into a mask RC Shoiso to mask the gate electrode. be. 1~
4 is a part similar to that in FIG. 6 is a region in which impurities are implanted at a high concentration. A heat-resistant gate material is required to withstand high-temperature annealing for electrically activating impurities implanted at a high temperature and to exhibit stable Schottky junction characteristics even after annealing. In addition, since this heat-resistant gate material is used as internal wiring in integrated circuits, the resistance value of the heat-resistant gate material is small even after high-temperature annealing, and the masking effect of the gate electrode material against high-concentration impurity implantation is sufficient. required.

Among the above, regarding the resistance value and maskability of the gate electrode material, the thicker the gate material, the less the resistance 1 cycle and the better the maskability, but increasing the thickness increases the gate electrode wiring step. , problems such as step breaks occur when forming upper layer wiring. From the above, it is desirable that the gate electrode material has the highest stability of Schottky junction. At present, tungsten (b), titanium tungsten (TiW), and tungsten silicide are being tried as heat-resistant gate materials. Regarding W, since the film that is actually formed has a columnar crystal structure, in the case of an amorphous structure, even when using a film thickness and implantation conditions that are considered to completely block implanted ions, it is difficult to implant. It has been confirmed that ion blocking is incomplete, and it is practically necessary to increase the thickness of the I/'i film, but in this case, the above-mentioned problem of the spacing occurs. -10,000 TiW, tungsten silicide +! In annealing at 850 DEG C. in which the impurities are forced to flow for vapor activation, the resistance value is reduced by a small amount of light, and the specific resistance value is about 150 to 300 μΩL:M.

9. This is a major problem in realizing GaAs integrated circuits that require high-speed manufacturing.

In the example in Figure 3, since an impurity layer is formed once again at the source/drain node, the gate material must be made of a material that can withstand high-temperature annealing, but in the M4 diagram, a heat-resistant material is used as the gate material. (a) is a schematic cross-sectional view of a device in the middle of manufacturing an FET immediately after a high concentration impurity is implanted into the source/drain layer. 11 is a semi-insulating substrate, 12 is an active layer, 13 is an insulating film, 14 is a resist, 15 is an insulating film, and the resist 14 is burnt to the absolute film 15, with some overetching. There is. 16 is a region into which impurities are implanted using the insulating film 15 as a mask. Figure 4(b) shows...After Figure 4(a), the old Naotoshi Mata-style element with the gate's opening is formed. After the structure shown in Figure 4 (ta) is obtained, the insulating film of 13 and the true loquat group 17 are added to the chain acid that is not removed by the resist of 14.
The resist No. 14 and the insulating film No. 15 are removed, and the implanted impurity material No. 916 is electrically activated by thermal annealing. Using the insulating film No. 17 as a mask, the insulation film No. 13 is formed. is etched to extend the GaAs radial surface, and a gate electrode 18 is formed by covering with gate material and shaping.
Figure (b)). After that, the insulating film 13, 17 at a predetermined location on the source/drain region is removed, and an ohmic electrode 1 is placed on the cough location.
By forming 9FET, the manufacturing of 9FET is completed (4th
Figure (C)). The PET described here has the advantage that it is not necessary to use a heat-resistant material as the gate material because the source/drain impurity layer is formed before the gate electrode is formed.

However, compared to the production of FhT shown in Figure 3!
! ! It has the disadvantage that the post-processes are complicated and the number of steps is long. In addition, the gate material plate layer 13
In the etching process, it is safe to perform dry etching because side etching of disconnected lines 1fi13 occurs, but it is not necessary to perform dry etching due to dry etching.
Problems related to loss of the As surface are considered to have the potential to be compressed.

In addition, the performance of GaAs J' m T is inferior to the back road, B
It is necessary to reduce S and make the Schottky junction characteristic more dimple, and it is also necessary to improve the reliability of the manufacturing process by reducing the resistance (Kg) of the gate material and simplifying and shortening the manufacturing process. However, at present, no manufacturing method has been found that satisfies all of these requirements.

An object of the invention is to provide a method for manufacturing a compound semiconductor device that overcomes the drawbacks of the prior art.

According to the present invention, after forming the entire 7 silicon film in contact with the active layer formed on the surface of the compound semiconductor substrate and forming the high melting point gold JI4 film on the silicon film, patterned resist)
5r, after etching and shaping only the melting point metal film on the k mask to form gate electrode wiring, the process of arranging the upper and lower silicon groups of the melting point metal on the silicide layer, 5r; In the method of the present invention, an impurity cut showing the same 4-region type as the 1iJf1 layer is used as a mask for game) If and love. From the ink injected into the high-temperature zone, the reduction of the resistance of the source/drain installation is beneficial, as well as the simplification and shortening of the 11'ET g manufacturing process. In addition, in the method of the present invention, since the high melting point metal silicide layer is present in contact with the compound-cut semiconductor operating layer, the sheet metal characteristic is deformed, and at the same time, the #ii melting point lid metal film on the silicide layer has low resistance. It has the advantage that the gate electrode wiring has low resistance, reflecting the fact that it is thin. Furthermore, since the method of the present invention injects an impurity having the same type as the active layer through the silicon film on the surface of the substrate, the silicon group has the advantage that it acts as a contamination prevention film against contamination from the implanted atmosphere gas. It also has In the method of the present invention, impurities exhibiting the same conductivity region as the active layer are implanted while a silicon film is present in the melting point metal film, and the silicon group of the metal film is enhanced by annealing. After changing to the melting point metal silicide, the active layer and the same conductor 4
When implanting an impurity that removes the mold, it will bite, but in either case silicon B! The blocking of implanted ions is incomplete due to the fact that A or a high melting point parallel silicide film is formed, and the presence of an interface between a silicon group or melting point metal silicide film and a melting point metal film. M is used because of the advantage that the lower limit thickness of the gate is smaller than that of the melting point metal layer.

An example of a multi-layer structure made of GaAsA4ESFhT according to the manufacturing method of the present invention will be explained using the fifth layer. Cr-doped semi-insulating G:a As substrate 51
was prepared, and 70% of Si ions were applied using the resist as a mask.
keV, 2x l 012at < 2 (D condition tell
A region 52 was formed in which the operation becomes "L" and the operation becomes "No" later. After removing the resist, 2% silicon group 53 was deposited by electron beam evaporation method.
After depositing 00A and further forming 400OA of Mo (g) and forming a resist pattern on the part that should become the gate electrode, using the resist pattern as a mask, the Mo film in the area not covered by the resist was coated with eel 4+U2 gas. A 1-1θ gate @ 54t was formed using a fully open dry etching method (Fig. 5 (a)).
The resist 55 was patterned so as to remain only on the silicon layer on the chain acid except for the impurity implantation region, which exhibits the same conductivity type as the hawk. Si ions were applied to this resist pattern and gate mask at 200 ieV 4X1013ff/V.
The impurity was implanted into the substrate through silicon g' under the following conditions to form a region 56 for impurity implantation (FIG. 5(b)). After removing the cyst/cyst, a silicon oxide film 57 is deposited on all the tracks by CVD method, and the implanted impurities are made into a foil by annealing at 850°C with phosphor gas. The entire silicon film silicide layer 58 was made to have a thickness of Km, and then the silicon oxide film and the silicon film on which the entire source/drain electrodes were to be formed were removed using a patterned resist as a mask to expose the GaAs surface. The Au-Ge and Ni films were evaporated, and A, u-Ge and Ni were left only in the locations using the 7-to-7 method, forming an Omitsu Kutun pole 59, and hydrogen gas was heated, for example, at 450°C for 1
hbT was photonized (Fig. 5 (C)).

The mutual conductance of a transistor whose gate amount and gate width are both 31-5.10 μm is, on average, l.
It showed a value of 70 m s/am.

In the above example, an example was shown in which an impurity having the same 4-electrode type as the active layer was implanted at a substitution degree in the presence of the silicon film under the MO layer. Prior to the step of injecting a large amount of impurity -# indicating the mold, 6
A transistor was manufactured by skipping the annealing process at 00°C for 20 minutes and adding a process to convert the silicon film of the Mo film into a silicide layer. Except for this additional annealing step at 600°C for 20 minutes, the manufacturing process described above and 'l! ! The settings are the same as those for the original version. The transconductance of the transistor manufactured in this way having a gate length and a gate width of 1.5 and 10 μm, respectively, is 170 m57111 on average.
It showed a high value of 1. In addition to the above samples, Silico/11
Mo film 1iooo, 20oO1600 on top of g20OA
F n 'r manufactured with a film thickness of 0A and silico ymo type i k 4f! ! LVI Od't l
The gate length was 20μIn and the gate width was 20μIn for each sample.
The threshold Z111 ratio of 30 transistors of 0 .mu.m was measured. The lower garment is disappointed, but as the MO film increases over the years, the absolute value of VT increases significantly as the layer thickness decreases, and the fluctuation of VT also increases. In a transistor in which a Mo film is formed on silicon/$20OA and the silicon film is converted to a silicide layer by high-temperature annealing, the absolute value of VT and its variation are small even when the upper layer Mod thickness becomes extremely thin. Does not increase. This is s6 once S
In the case of NLo conversion, blocking of implanted ions during i-implantation is poor even at a film thickness of 4000λ, but
Silicide tribe and M.

This is thought to be due to the fact that in the case of a film with a thickness of 2 fII, even in the case of an iVo conversion thickness of 00λ, the blocking of implanted ions is effective.

In the above embodiments, the silicon group is Ga other than the source/drain ohmic electrode metal and the gate electrode.
Although an example has been shown where it is left on the As surface, if desired, it is also possible to remove it using, for example, a resist as a mask, after injecting high-concentration impurity ions or after temperature annealing.

In this case, it is desirable to leave a silicon film with a certain width surrounding the gate electrode. In the above examples, the case where Mod was used as the high melting point metal was described, but W%
Exactly the same effect can be obtained even when a metal with a melting point of 1I4t' such as Ti1Ta is used.

In addition, in the above embodiment, the field of UaAs was shown as a scattering, but the IX formed on the semi-insulating InJ'
It has 7-3 IXION electron-atft members on LnP epitaxial mass and Chibi-related Ink' which generate 10 oi electrons at once.''Q, 5
3. ``When we used the method of the present invention on 0.47As pigeons, we were able to obtain stable Schottky characteristics even during 1ib11A annealing at 850°C for 20 minutes.

[Brief explanation of drawings]

Figures 1, 2, and 3 are conventionally well-known G a A
This shows the IF surface diagram of the 5FET Matata style, l is hanpojojo, 2 is the operating layer, and 3 is game)! Unfortunately, 4 is the sauce.
The drain electrode 5 is a surface depletion layer. Figures 4 (a), (b), and (C) show FE by the conventional method.
FIGS. 3A and 3B are cross-sectional views of Fk and T shown in sequence following the main steps in the diagram C for explaining the Tfi manufacturing method. In the figure, 11 is a semi-insulating substrate, 12 is an active layer, 13 is an insulating film, 14 is a resist, and 15 is a semi-insulating substrate.
1 is an insulating film, 16 is an ion-implanted region to be impurized once, 17 is an absolute M film, 18 is a gate electrode, and 19 is a source/drain electrode. FIGS. 5(a), (b), and (C) are diagrams for explaining how a transistor is backtracked using the method of the present invention, and show a schematic cross-sectional view of a transistor following the song of the main broken air. It is something that 51 is a semi-insulating substrate, 52
53 is a fabrication layer, 53 is a silicon group, 54 is a #IA point metal film, 55 is a resist group, 56 is an impurity injection region, 5
7 is an insulating film, 58 is a low melting point metal silicide film, and 59 is a source/drain film. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] The compound was formed on a similar working layer to form a silicon/gland, and a Ksbm dot W4 gland was formed on the cough silicone, and a patterned resist was applied to the gold mask to form a dot metal. Only the exhibition is etched and distorted and the gate 1 love wiring and no f
After c, a step of implanting an impurity having the same shape as that of the active layer into the desired region in the substrate using the Ekishima melting point metal group as a mask, and annealing to remove the silicon under the melting point metal film. 1. A method for manufacturing a compound semiconductor device, comprising the step of converting IIX into a melting point metal 7 reside film.