JPS6235273B2 - - Google Patents
Info
- Publication number
- JPS6235273B2 JPS6235273B2 JP5387578A JP5387578A JPS6235273B2 JP S6235273 B2 JPS6235273 B2 JP S6235273B2 JP 5387578 A JP5387578 A JP 5387578A JP 5387578 A JP5387578 A JP 5387578A JP S6235273 B2 JPS6235273 B2 JP S6235273B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- impurity concentration
- mode
- bidirectional thyristor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009792 diffusion process Methods 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 18
- 230000002457 bidirectional effect Effects 0.000 claims description 17
- 238000005275 alloying Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 238000005219 brazing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 239000000956 alloy Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 230000007423 decrease Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010828 elution Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/747—Bidirectional devices, e.g. triacs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
この発明は、そのゲート特性の改善を図る双方
向サイリスタの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bidirectional thyristor that improves its gate characteristics.
第１図は従来の双方向サイリスタを示す断面図
である。 FIG. 1 is a sectional view showing a conventional bidirectional thyristor.
図において、１は第一導電型層３と第二導電型
層５に低抵抗接触している第一電極T1、２は第
一導電型層４と第二導電型層５に低抵抗接触して
いるゲート電極、６は第一導電型の高比抵抗層、
９は第一導電型層８と第二導電型層７に低抵抗接
触している第二電極T2である。 In the figure, 1 is the first electrode T 1 which is in low resistance contact with the first conductivity type layer 3 and the second conductivity type layer 5, and 2 is the first electrode T 1 which is in low resistance contact with the first conductivity type layer 4 and the second conductivity type layer 5. 6 is a high resistivity layer of the first conductivity type,
9 is a second electrode T 2 that is in low resistance contact with the first conductivity type layer 8 and the second conductivity type layer 7.
なお、各第一導電型層３，４，８はリン拡散に
よつて形成され、その合金前の表面濃度及び拡散
深さは同じであつたものである。 Note that each of the first conductivity type layers 3, 4, and 8 was formed by phosphorus diffusion, and had the same surface concentration and diffusion depth before alloying.
双方向サイリスタのスイツチングモードは４つ
あり、それらを仮にそれぞれ、、、モー
ドと呼ぶ。一般にはこれらの内の及びモード
が使われる。よつて、及びモードの説明をす
る。 There are four switching modes for bidirectional thyristors, which are tentatively called modes. Generally, modes 1 and 2 among these are used. Therefore, I will explain the mode.
モードＩGT：第二電極９を第一電極１に対し
正電位にし、かつゲート電極２を第一電極１に対
し正電位にした時の双方向サイリスタがオンする
のに必要なゲート電流。 Mode I GT : Gate current required to turn on the bidirectional thyristor when the second electrode 9 is at a positive potential with respect to the first electrode 1 and the gate electrode 2 is at a positive potential with respect to the first electrode 1.
モードＩGT：第二電極９を第一電極１に対し
負電位にし、かつゲート電極２を第一電極１に対
し負電位にした時の双方向サイリスタがオンする
のに必要なゲート電流。 Mode I GT : Gate current required to turn on the bidirectional thyristor when the second electrode 9 is set to a negative potential with respect to the first electrode 1 and the gate electrode 2 is set to a negative potential with respect to the first electrode 1.
従来の双方向サイリスタでは、各第一導電型層
３，４，８の合金前の表面不純物濃度及び拡散深
さは同じである。よつて、第二電極９の合金に
Alを使用する場合、層８のＮ型不純物が溶出す
ることにより、層８の表面不純物濃度及び拡散深
さは、層３，４のそれらに比べて小さくなる。こ
のため、層８，７及び６からなるNPNトランジ
スタの電流増巾率αnpnが小さくなり前述のモ
ードＩGTが増大する。また、モードスイツチン
グ機構はリモートゲート構造を使用しているた
め、モードＩGTはＩモードＩGTに比べて非常に
大きい。 In a conventional bidirectional thyristor, each first conductivity type layer 3, 4, 8 has the same surface impurity concentration and diffusion depth before alloying. Therefore, the alloy of the second electrode 9
When Al is used, the surface impurity concentration and diffusion depth of layer 8 become smaller than those of layers 3 and 4 due to the elution of N-type impurities in layer 8 . Therefore, the current amplification rate αnpn of the NPN transistor composed of layers 8, 7, and 6 becomes small, and the above-mentioned mode I GT increases. Also, since the mode switching mechanism uses a remote gate structure, mode I GT is much larger than I mode I GT .
この発明はこのような点に鑑みてなされたもの
で、第二電極を合金してもゲート特性が劣化する
ことのない双方向サイリスタの製造方法を提供す
ることを目的とする。 The present invention has been made in view of these points, and it is an object of the present invention to provide a method for manufacturing a bidirectional thyristor in which the gate characteristics do not deteriorate even when the second electrode is alloyed.
第２図はこの発明による双方向サイリスタの一
実施例を示す断面図である。 FIG. 2 is a sectional view showing an embodiment of a bidirectional thyristor according to the present invention.
図において、第１図と同一符号は夫々同一又は
相当部分を示しており、第１図と異なるところ
は、第二電極９との合金前の層８の表面不純物濃
度が層３，４の表面不純物濃度の1.7倍以上であ
り、また層８の拡散深さが層３，４の拡散深さよ
り５μｍ以上深くなつている。 In the figure, the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and the difference from FIG. 1 is that the surface impurity concentration of the layer 8 before alloying with the second electrode 9 is The impurity concentration is 1.7 times or more, and the diffusion depth of layer 8 is deeper than that of layers 3 and 4 by 5 μm or more.
つまりＮ型拡散層３，４と比べて表面不純物濃
度及び拡散深さがそれぞれ1.7倍以上及び５μｍ
以上のＮ型拡散層８を形成した後に、アルミニウ
ムを含むろう材により合金化して第二電極９をＮ
型拡散層８に接触させた双方向サイリスタであ。 In other words, compared to N-type diffusion layers 3 and 4, the surface impurity concentration and diffusion depth are 1.7 times or more and 5 μm, respectively.
After forming the above N-type diffusion layer 8, the second electrode 9 is formed by alloying with a brazing material containing aluminum.
This is a bidirectional thyristor that is in contact with the type diffusion layer 8.
このように、層８の合金前の表面不純物濃度及
び拡散深さが層８，４のそれらに比べて大きくな
つていると、第二電極９の合金にA1を使用した
場合でも、層８のシリコン及び不純物が溶出して
層８の表面不純物濃度及び拡散深さが合金前より
小さくなつても、層３，４のそれらより小さくな
らず、モードＩGT値はＩモードＩGT値に近づ
く。 In this way, if the surface impurity concentration and diffusion depth of layer 8 before alloying are larger than those of layers 8 and 4, even if A1 is used as the alloy of second electrode 9, Even if silicon and impurities are eluted and the surface impurity concentration and diffusion depth of layer 8 are smaller than before alloying, they are not lower than those of layers 3 and 4, and the mode I GT value approaches the I mode I GT value.
また、層８，７及び６からなるトランジスタの
αnpnが層３，５及び６からなるNPNトランジス
タのαnpnより大きい為、（これはモードスイ
ツチング機構がリモートゲート構造を使用してい
る事に起因する）モードＩGTの増大を減少させ
る事ができる。即ち、モードＩGTをＩモードＩ
GTに近づける事ができる。 Also, since αnpn of the transistor consisting of layers 8, 7, and 6 is larger than αnpn of the NPN transistor consisting of layers 3, 5, and 6 (this is due to the mode switching mechanism using a remote gate structure). ) The increase in mode I GT can be reduced. That is, mode I GT is changed to mode I
It can be brought closer to GT .
すなわち、第二電極９の合金にA1を使用した
場合、A1とSiの合金化によつて層８の厚さが減
少するが、５μｍ以上小さくなることはなく、ま
た、表面から５μｍの所の不純物濃度は表面不純
物濃度の1/1.7以上あるので、上述の如く、合金
前の層８の表面不純物濃度及び拡散深さをそれぞ
れ1.7倍以上及び５μｍ以上大きくすれば、第二
電極９の合金にA1を使用しても層８の表面不純
物濃度及び拡散深さが第一電極１側の層３，４の
それよりも大きくなるので、モードＩGTはＩモ
ードＩGTに近づく。 That is, when A1 is used as the alloy for the second electrode 9, the thickness of the layer 8 decreases due to the alloying of A1 and Si, but it does not decrease by more than 5 μm, and the thickness of the layer 8 at a distance of 5 μm from the surface decreases. Since the impurity concentration is 1/1.7 or more of the surface impurity concentration, as described above, if the surface impurity concentration and diffusion depth of the layer 8 before alloying are increased by 1.7 times or more and by 5 μm or more, the alloy of the second electrode 9 Even if A1 is used, the surface impurity concentration and diffusion depth of layer 8 will be larger than those of layers 3 and 4 on the first electrode 1 side, so mode I GT approaches I mode I GT .
なお、このような現象は層３，４，８の形成が
リンをテポジシヨンした後ペネトレーシヨンする
方法による場合に特に顕著である。 Incidentally, such a phenomenon is particularly noticeable when the layers 3, 4, and 8 are formed by a method in which phosphorus is deposited and then penetrated.
第３図及び第４図はこの発明によつて製造され
た双方向サイリスタの他の態様を示す断面図であ
る。 3 and 4 are cross-sectional views showing other embodiments of the bidirectional thyristor manufactured according to the present invention.
第３図に示した双方向サイリスタは、層４の真
下の部分のみの層８の合金前の不純物濃度及び拡
散深さが、層８の他の部分及び層３，４のそれら
に比べてそれぞれ1.7倍以上及び５μｍ以上大き
くなつている。 The bidirectional thyristor shown in FIG. 3 has a pre-alloy impurity concentration and a diffusion depth of the layer 8 only in the portion immediately below the layer 4 compared to other portions of the layer 8 and layers 3 and 4, respectively. It has become larger by more than 1.7 times and by more than 5 μm.
第４図に示した双方向サイリスタは、層８が２
つの層８ａ，８ｂに分離され、層４の真下にある
層８ｂの合金前の表面不純物濃度及び拡散深さが
層８，４，８ａのそれらに比べてそれぞれ1.7倍
以上及び５μｍ以上大きくなつている。 The bidirectional thyristor shown in FIG.
The surface impurity concentration and diffusion depth before alloying of layer 8b, which is separated into two layers 8a and 8b directly below layer 4, are 1.7 times or more and 5 μm or more larger than those of layers 8, 4, and 8a, respectively. There is.
この第３図及び第４図に示した双方向サイリス
タにおいても、モードで動作するサイリスタ部
の第二電極９側のエミツタ層の合金前の表面不純
物濃度及び拡散深さが、Ｉモードで動作するサイ
リスタ部の第一電極１側のエミツタ側とリモート
ゲート層４の表面不純物濃度及び拡散深さより大
きくなつているので、第１図の場合と同様の効果
が得られる。 In the bidirectional thyristor shown in FIGS. 3 and 4 as well, the surface impurity concentration and diffusion depth before the alloy of the emitter layer on the second electrode 9 side of the thyristor section that operates in the I mode operate in the I mode. Since the surface impurity concentration and diffusion depth are greater than those of the emitter side of the first electrode 1 side of the thyristor portion and the remote gate layer 4, the same effect as in the case of FIG. 1 can be obtained.
第１図は従来の双方向サイリスタを示す断面
図、第２図はこの発明の製造方法による双方向サ
イリスタの一実施例を示す断面図、第３図及び第
４図はこの発明の製造方法による双方向サイリス
タの他の態様を示す断面図である。
図において、１は第一電極T1、２はゲート電
極、３，４及び８はそれぞれ第一導電型層、５及
び７はそれぞれ第二導電型層、６は第一導電型の
高比抵抗層、９は第二電極T2である。なお、図
中同一符号はそれぞれ同一または相当部分を示
す。
FIG. 1 is a sectional view showing a conventional bidirectional thyristor, FIG. 2 is a sectional view showing an embodiment of a bidirectional thyristor according to the manufacturing method of the present invention, and FIGS. 3 and 4 are sectional views according to the manufacturing method of the present invention. FIG. 7 is a sectional view showing another aspect of the bidirectional thyristor. In the figure, 1 is the first electrode T 1 , 2 is the gate electrode, 3, 4 and 8 are each a first conductivity type layer, 5 and 7 are each a second conductivity type layer, and 6 is a high specific resistance of the first conductivity type. Layer 9 is the second electrode T2 . Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
１のＮ型拡散層を形成させる工程、上記半導体基
板の他面に上記第１のＮ型拡散層と比較して表面
不純物濃度及び拡散深さがそれぞれ1.7倍以上及
び５μｍ以上の遠隔ゲートを構成する第２のＮ型
拡散層を形成させる工程、この第２のＮ型拡散層
面にアルミニウムを含むろう材により合金化して
電極を接触させる工程を含む双方向サイリスタの
製造方法。1. Forming a first N-type diffusion layer constituting a junction gate on one surface of the semiconductor substrate, and forming a first N-type diffusion layer on the other surface of the semiconductor substrate with a surface impurity concentration and diffusion depth lower than that of the first N-type diffusion layer. A step of forming a second N-type diffusion layer constituting a remote gate of 1.7 times or more and a distance of 5 μm or more, respectively, and a step of alloying the surface of the second N-type diffusion layer with a brazing material containing aluminum and contacting an electrode. A method of manufacturing a bidirectional thyristor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5387578A JPS54145484A (en) | 1978-05-06 | 1978-05-06 | Two-way thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5387578A JPS54145484A (en) | 1978-05-06 | 1978-05-06 | Two-way thyristor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54145484A JPS54145484A (en) | 1979-11-13 |
| JPS6235273B2 true JPS6235273B2 (en) | 1987-07-31 |
Family
ID=12954910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5387578A Granted JPS54145484A (en) | 1978-05-06 | 1978-05-06 | Two-way thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54145484A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4939565A (en) * | 1987-04-09 | 1990-07-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JPH0715992B2 (en) * | 1989-11-14 | 1995-02-22 | 新電元工業株式会社 | Bidirectional 2-terminal thyristor |
| JPH0685437B2 (en) * | 1990-02-16 | 1994-10-26 | 新電元工業株式会社 | Bidirectional 2-terminal thyristor |
-
1978
- 1978-05-06 JP JP5387578A patent/JPS54145484A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54145484A (en) | 1979-11-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4987562A (en) | Semiconductor layer structure having an aluminum-silicon alloy layer | |
| JPH01103876A (en) | Insulated-gate semiconductor device | |
| JPS60194558A (en) | Manufacture of semiconductor device | |
| US4542400A (en) | Semiconductor device with multi-layered structure | |
| JPS62102559A (en) | Semiconductor device and manufacture thereof | |
| JPS6235273B2 (en) | ||
| GB2168848A (en) | Semiconductor devices | |
| JPS61210668A (en) | Semiconductor device | |
| JP2750803B2 (en) | Bidirectional thyristor | |
| JPS6141248Y2 (en) | ||
| JPS5938730B2 (en) | Manufacturing method of semiconductor device | |
| JP2724490B2 (en) | Manufacturing method of gate turn-off thyristor | |
| JPS59101868A (en) | Semiconductor device having schottky barrier and low resistance contact, and manufacture thereof | |
| JPS5984468A (en) | Semiconductor device | |
| JP2843569B2 (en) | Semiconductor device | |
| JPS62160761A (en) | Semiconductor device | |
| JPH0317225B2 (en) | ||
| JPS60176249A (en) | Semiconductor device having buried area | |
| JPH05243368A (en) | Semiconductor device | |
| JPH0883918A (en) | Semiconductor device | |
| JPS58164241A (en) | Manufacture of semiconductor device | |
| JPH05235011A (en) | Semiconductor device | |
| JPS59231871A (en) | Semiconductor device | |
| JPH0669091B2 (en) | Method for manufacturing semiconductor device | |
| JPH048955B2 (en) |