JPS59101868A - Semiconductor device having schottky barrier and low resistance contact, and manufacture thereof - Google Patents
Semiconductor device having schottky barrier and low resistance contact, and manufacture thereofInfo
- Publication number
- JPS59101868A JPS59101868A JP21130982A JP21130982A JPS59101868A JP S59101868 A JPS59101868 A JP S59101868A JP 21130982 A JP21130982 A JP 21130982A JP 21130982 A JP21130982 A JP 21130982A JP S59101868 A JPS59101868 A JP S59101868A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 230000004888 barrier function Effects 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000000203 mixture Substances 0.000 claims abstract description 5
- 239000007772 electrode material Substances 0.000 claims abstract 2
- 238000009826 distribution Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 7
- 238000001259 photo etching Methods 0.000 abstract description 7
- 238000005275 alloying Methods 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910021339 platinum silicide Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に係り、特に半導体基体に低抵抗接
触する電極と半導体基体にショットキー障壁を形成して
接触する電極とを具備する半導体装置及びその製造方法
に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device comprising an electrode that makes low resistance contact with a semiconductor substrate and an electrode that makes contact with the semiconductor substrate by forming a Schottky barrier. and its manufacturing method.
半導体基体に低抵抗接触する電極と、半導体基体にショ
ットキー障壁を形成する様に接触する電極とを具備する
半導体装置の一つとして、ショットキーダイオードをク
ランプダイオードに用いるショットキーＴＴＬ回路（以
下５ＴＴＬ （ＳｃｈｏｔｔｋｙＴｒａｎｓｉｓｔｏｒ
’ｐｒａｎｓｉｓｔｏｒ Ｌｏｇｉｃ）と略す）が、
従来広く用いられている。電極と半導体基体との整流接
触を利用するショットキーダイオード（以下Ｓ Ｂ Ｄ
（８ｃｈｏｔｔｋｙ １３ａｒｒｉｅｒ Ｄｉｏｄｅ
）ト略す）は、順方向電圧降下が低いほど回路スピー
ドの劣化に対する余裕度が大きく、または素子面積を小
さくできる。この順方向特性を決めるのは、電極に用い
る金属と半導体基体であるＮ型シリコンとの仕事函数の
差（以下φＢと略す）であシ、φＢが小さいほど望まし
い。A Schottky TTL circuit (hereinafter referred to as 5TTL) that uses a Schottky diode as a clamp diode is one of the semiconductor devices equipped with an electrode that contacts a semiconductor substrate with low resistance and an electrode that contacts the semiconductor substrate to form a Schottky barrier. (Schottky Transistor
'Pransistor Logic') is
Conventionally widely used. A Schottky diode (hereinafter referred to as SBD) uses rectifying contact between an electrode and a semiconductor substrate.
(8chottky 13arrier Diode
), the lower the forward voltage drop, the greater the margin against deterioration of circuit speed, or the smaller the element area. This forward characteristic is determined by the difference in work function (hereinafter abbreviated as φB) between the metal used for the electrode and the N-type silicon that is the semiconductor substrate, and the smaller φB is, the more desirable it is.
ところで、従来低電カシヨツトキーＴＴＬ（ＬＳＴＴＬ
）に用いる電極金属としては、φＢの低電ｐｕｒｅＡｔ
が一般に用いられる（φｖｒ ＝０．６７ ｅ Ｖ〜０
．７２ｅＶ）。第１図はＰ ｕ ｒｅ Ａ を電極をＳ
ＢＤ電極（６）およびバイポーラトランジスタのエミッ
タ電極（５）に用いた従来例の断面構造を示している。By the way, the conventional low-voltage key TTL (LSTTL)
) As the electrode metal used for
is generally used (φvr = 0.67 e V~0
．． 72eV). Figure 1 shows P u re A and the electrode S
The cross-sectional structure of a conventional example used for a BD electrode (6) and an emitter electrode (5) of a bipolar transistor is shown.
１はコレクタ層となるＮ型りｊ半導体基体、２はＰ型ベ
ース層、３はＮ型エミツタ層、４は酸化膜、５はＮ型エ
ミツタ層３に低抵抗接触するｐｕｒｅＡｌ電極、６は半
導体基体１の主表面に露出するＰ型ベース層２、Ｎ型エ
ミツタ層とショットキー障壁が形成する様に接触するｐ
ｕｒｅＡｔ電極である。1 is an N-type semiconductor substrate serving as a collector layer, 2 is a P-type base layer, 3 is an N-type emitter layer, 4 is an oxide film, 5 is a pure Al electrode in low resistance contact with the N-type emitter layer 3, and 6 is a semiconductor P-type base layer 2 exposed on the main surface of substrate 1 and P-type base layer 2 in contact with N-type emitter layer to form a Schottky barrier.
This is a ureAt electrode.
ところで、ｐｕｒｅＡｘｔ電極に用いた場合、ｐｕｒｅ
ＡｔとＳｉ基板との反応によシ、浅いＰＮ接合の場合に
は耐圧劣化が生じる。通常０．８μｍ以上の接合深さく
第１図のエミツタ層３の接合深さ）にしか適用できない
。By the way, when used for pure Axt electrode, pure
Due to the reaction between At and the Si substrate, breakdown voltage deterioration occurs in the case of a shallow PN junction. Usually, it can be applied only to a junction depth of 0.8 μm or more (the junction depth of the emitter layer 3 in FIG. 1).
一方、近年、高集積化のためにＰＮ接合深さが浅くなシ
（例えばエミッタ深さ０．４μｍ）、これに対する電極
としては、５ｉ（ｉ−数％含んたＡｌ（以下ｈｔ−ｓｔ
と略す）が用いられてきている。On the other hand, in recent years, due to high integration, the PN junction depth has become shallow (e.g. emitter depth 0.4 μm), and electrodes for this have become 5i (hereinafter ht-st) containing several % of aluminum.
) has been used.
この場合、Ａｔ中に含まれた３ｉが、ＡｔとＳｉ基板と
の反応を防ぐ。しかし、ｈｔ＊ｓｉで形成されたＳＢＤ
の電極は、電極と３ｉとの界面にＳｉの析出が生じ□る
現象等のため、見かけ上のφＢに０．８ｅＶ以上になっ
てしまう。第２図は従来例であるところの電極としてｈ
ｔ−ｓｉを用いた場合の断面構造を示している。５／、
６／は夫夫ｈｔ−ｓ：によるエミッタおよび８ＢＤ電極
であシ、第１図と同一符号は同−物及び相当物を示す。In this case, 3i contained in At prevents the reaction between At and the Si substrate. However, SBD formed with ht*si
In the case of the electrode, the apparent φB becomes 0.8 eV or more due to the phenomenon that Si is precipitated at the interface between the electrode and 3i. Figure 2 shows a conventional example of electrode h.
The cross-sectional structure when using t-si is shown. 5/,
6/ is the emitter and 8BD electrode according to Hufu ht-s:, and the same reference numerals as in FIG. 1 indicate the same and equivalent parts.
浅いＰＮ接合に適用できる電極構造としては、白金シリ
サイド（ｐｔ−ｓｉ）も用いられているがφＢは大きイ
（０，８５ｅＶ）。Platinum silicide (PT-Si) is also used as an electrode structure applicable to shallow PN junctions, but φB is large (0.85 eV).
尚、半導体基体がＰ型の場合、ＳＢＤ穏ではφＢが大き
くすることが望まれるが（例えば、Ａｔではｏ、＋ｘｅ
ｖ、ｐｔｓｔでは０．２５ｅＶ、Ｎ型の場合と同様に、
浅いＰＮ接合に適用でき、しかもＳＢＤ部ではφＢが大
きくできる金属は卸られていない。Note that when the semiconductor substrate is P type, it is desirable to increase φB in the case of moderate SBD (for example, in case of At, o, +xe
v, ptst is 0.25 eV, similar to the N type case,
There are no metals on the market that can be applied to shallow PN junctions and can increase φB in the SBD portion.
以上の様に、従来例に於いては、順方向電圧降下が低い
こと、また、浅いＰＮ接合の耐圧劣化が生じないことの
２点を同時には満足できなかった。As described above, in the conventional example, it was not possible to simultaneously satisfy two points: low forward voltage drop and no deterioration of the withstand voltage of the shallow PN junction.
〔発明の目的〕
本発明の目的とするところは上記欠点を除去し、順方向
電圧降下が低く、かつ浅いＰＮ接合の耐圧劣化が生じな
い半導体装置及び工程数が少なく経済的な半導体装置の
製造方法を提供することにある。[Object of the Invention] The object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor device with a low forward voltage drop and no deterioration of the withstand voltage of a shallow PN junction, and to manufacture an economical semiconductor device with a small number of steps. The purpose is to provide a method.
上記目的を達成する本発明半導体装置の特徴とするとこ
ろは、主表面を有し、上記主表面に露出する第１導電型
の第１の領域、上記第１の領域との間に形成されるＰＮ
接合が上記主表面に終端するように上記第１の領域内に
形成される第２導電型の第２の領域、を少なくとも有す
る半導体基体と、上記主表面に於いて上記第２の領域に
低抵抗接触する第１の電極と、上記第２の領域を除く上
記主表面の少なくとも一部にショットキー障壁が形成さ
れる様に接触する第２の電極とを具備するものに於いて
、上記第１の電極は上記第２の電極の材料と上記半導体
基体の材料との混合物からなることにある。The semiconductor device of the present invention that achieves the above object is characterized by having a main surface, a first region of a first conductivity type exposed on the main surface, and a first region formed between the first region and the first region. P.N.
a semiconductor substrate having at least a second region of a second conductivity type formed within the first region such that a bond terminates at the main surface; A first electrode that contacts resistively and a second electrode that contacts at least a portion of the main surface excluding the second region so as to form a Schottky barrier. The first electrode is made of a mixture of the material of the second electrode and the material of the semiconductor substrate.
また、本発明半導体装置の製造方法の特徴とするところ
は、上記第１の電極は、上記第２の電極の材料からなる
第１層と、上記第１層上に形成される上記半導体基体の
材料、または上記第２の電極の材料と上記半導体基体の
材料との混合物からなる第２層とを積層して形成し、上
記第２層中の半導体基体の材料が上記第１層及び上記第
２層中にほぼ均一に濃度分布し、かつ上記第２の電極と
〔発明の実施例〕
以下本発明を実施例に基づき詳細に説明する。Further, the method for manufacturing a semiconductor device of the present invention is characterized in that the first electrode includes a first layer made of the material of the second electrode and a semiconductor substrate formed on the first layer. or a second layer made of a mixture of the material of the second electrode and the material of the semiconductor substrate, and the material of the semiconductor substrate in the second layer is the same as the material of the first layer and the material of the semiconductor substrate. [Embodiments of the Invention] The present invention will be described in detail below based on Examples.
第３図は本発明半導体装置の一実施例であるＳＢＤ付の
ＮＰＮ）ランジスタの断面概略図である。FIG. 3 is a schematic cross-sectional view of an NPN transistor with SBD which is an embodiment of the semiconductor device of the present invention.
１はＮ型コレクタ層となる一対の主表面を有する半導体
基体であるＮ型Ｓｉ基体、２はＮ型Ｓｉ基体１の一方の
主表面に露出し、基体１ＯＮ型層との間に形成されるＰ
Ｎ接合が基体１の一方主表面に終端するように形成され
るＰ型ベース層、３はＰ型代−ス層２との間に形成され
るＰＮ接合が基体１の一方の主表面に終端するよりにＰ
型代−ス層２内に形成されるＮ型エミツタ層、４は５ｉ
ｏｚ等の絶縁膜、１０は基体の一方の主表面に露出する
Ｎ型コレクタ層１、Ｐ型ベース層２にショットキー障壁
が形成される様に接触するｐｕｒｅＡｔからなるＳＢＤ
電極、１１は基体の一方の主表面に露出するＮ型エミツ
タ層と低抵抗接触するｈｔ−ｓｔからなるエミッタ電極
である。1 is an N-type Si substrate which is a semiconductor substrate having a pair of main surfaces serving as an N-type collector layer; 2 is exposed on one main surface of the N-type Si substrate 1 and is formed between the substrate 1 and the ON-type layer; P
A P-type base layer 3 is formed such that an N-junction terminates on one main surface of the substrate 1; Rather than P
The N-type emitter layer 4 formed in the mold base layer 2 is 5i.
10 is an SBD made of pure At, which is in contact with an N-type collector layer 1 exposed on one main surface of the substrate and a P-type base layer 2 so as to form a Schottky barrier.
The electrode 11 is an emitter electrode made of ht-st that makes low resistance contact with the N-type emitter layer exposed on one main surface of the substrate.
本実施例に於いては、ＳＢＤ電極１０はｐｕｒｅＡ７か
らなるので、ＮＷシリコン基体１に対してφＢを小さく
することができ、順方向電圧降下が低くなる。また、エ
ミッタ電極１１はＡｔ ｍ Ｓ ｉからなるのでＰ型代
−ス層２とＮ型エミツタ層３との間に形成されるＰＮ接
合を浅くできかつ耐圧劣化が生じない。In this embodiment, since the SBD electrode 10 is made of pure A7, φB can be made smaller than that of the NW silicon substrate 1, and the forward voltage drop is reduced. Furthermore, since the emitter electrode 11 is made of AtmSi, the PN junction formed between the P-type substitute layer 2 and the N-type emitter layer 3 can be made shallow, and no breakdown voltage deterioration occurs.
第４図に第３図の実施例の製造方法の一例の工程図を示
す。FIG. 4 shows a process diagram of an example of the manufacturing method of the embodiment shown in FIG.
公知の方法でＰｉベース層、Ｎ型エミツタ層が形成され
た半導体基体の主表面上の絶縁膜を電極形成部分のみを
公知のエツチング方法にて除去し、ｐ ｕ ｒ ｅ Ａ
ｔを蒸着する。ＳＢＤ電極をホトエツチングを用いて形
成した後、Ａｚ−ｓｉｉ蒸着し、エミッタ電極をホトエ
ツチングを用いて形成し、コンタクトアロイを行なう。The insulating film on the main surface of the semiconductor substrate on which the Pi base layer and the N-type emitter layer were formed by a known method was removed by a known etching method only in the electrode formation portion, and then p
Deposit t. After the SBD electrode is formed using photoetching, Az-sii vapor deposition is performed, the emitter electrode is formed using photoetching, and contact alloying is performed.
第５図に第３図の実施例の製造方法の他の例である工程
図とそれに対応する概略断面図を示す。FIG. 5 shows a process diagram of another example of the manufacturing method of the embodiment shown in FIG. 3 and a corresponding schematic sectional view.
バイポーラトランジスタの形成された基体にホトエツチ
ング全施し、コンタクト窓開け（第５図（ａ） ） ｆ
行なった後、ｌ） ｕ ｒ ｅＡｔ７ｅ Ｑ−７μ”
ＸＳｌを５％含んだＡｔ−５ｉｓを０．３μｍ同一装置
内で連続して蒸着する（第５図（ｂ））。この様な連続
蒸着は、例えば電子ビーム蒸着装置において、蒸着用ソ
ースとしてｐｕｒｅｈｔとＳｉ１電子銃として２個用意
し、ｐｕｒｅｈｔ ２蒸着しながら途中からＳｉを混入
させれば良い。また、スパッタ装置を用いる場合には、
ｐｕｒｅＡ７のターゲットとｈｔ−ｓｉのターゲラトラ
同じ装置内に用意する事で可能である。The entire substrate on which the bipolar transistor is formed is photo-etched, and a contact window is opened (Fig. 5(a)) f
After doing this, l) ur eAt7e Q-7μ”
At-5is containing 5% XSl was continuously deposited to a thickness of 0.3 μm in the same apparatus (FIG. 5(b)). Such continuous evaporation can be carried out by, for example, using an electron beam evaporation apparatus, by preparing two electron guns, one pure as an evaporation source and the other as an Si1 electron gun, and mixing Si in the middle of the evaporation of pure 2. In addition, when using a sputtering device,
This is possible by preparing the pure A7 target and the ht-si target controller in the same device.
すなわち、第５図（ｂ）に相同する工程は、１回の蒸着
に等しい。なお、蒸着膜の構造としては、ｐｕｒｅＡｔ
（１μｍ）の上にＳｉのみを蒸着（０，１μｍ）しても
よい。That is, the process homologous to FIG. 5(b) is equivalent to one vapor deposition. The structure of the deposited film is pureAt
(1 μm), only Si may be deposited (0.1 μm).
次に、ホトエツチング工程によ、９．５ＢＤＱ部上のＡ
ｚ−ｓｉ層のみ全除去する（第５図（Ｃ））。Next, A on the 9.5BDQ section is removed by a photo-etching process.
Only the z-si layer is completely removed (FIG. 5(C)).
続いて、ホトエツチングによシ全体の電極パターンを形
成する（第５図（ｄ））。この結果、ＳＢＤ部にはｐｕ
ｒｅｈｔ電極１０が、エミッタ電極部分にはｐ ｕ ｒ
ｅＡｔ／Ａｔ−８ｉ （７） ２層膜の電極７，８が
形成される。Subsequently, the entire electrode pattern is formed by photo-etching (FIG. 5(d)). As a result, pu
reht electrode 10, emitter electrode part is p u r
eAt/At-8i (7) Two-layer film electrodes 7 and 8 are formed.
この後、コンタクトアロイ（４ｓｏｃ、３ｏ分、Ｈ２雰
囲気）を行なう。この結果、ＳＢＤ部はφｍ ＝０．７
２ ｅＶの接合が形成され、一方エミッタ部（’ａ合深
す０．４ ｐ ｍ ） ｃＤ電極１１は、ｈｔ−ｓｉか
らのＢｉの拡散によシＳｉがほば均一に濃度分布するＡ
ｔ−５ｉ（ｓｉ含有量約１５％）となるため電極とＳｉ
半導体基体との反応は殆んど進まず、浅いＰＮ接合に対
する耐圧劣化の問題は生じない（第５図（ｅ））。After this, contact alloying (4 soc, 3 o minutes, H2 atmosphere) is performed. As a result, the SBD section has φm =0.7
A junction of 2 eV is formed, while the emitter part ('a junction depth 0.4 pm) cD electrode 11 is formed of an A layer with a nearly uniform concentration distribution of Si due to the diffusion of Bi from the ht-Si.
t-5i (Si content approximately 15%), so the electrode and Si
The reaction with the semiconductor substrate hardly progresses, and the problem of breakdown voltage deterioration due to shallow PN junctions does not occur (FIG. 5(e)).
以上説明してきた様に、本実施例によれば、第４図に示
した例に比べ、電極蒸着回数が１回で済むため、工程数
の低減の利点を持ち、また、コンタクト抵抗のばらつき
等の問題も生じない。すなわち、比較的簡単な工程でφ
βの低いＳＢＤと、浅い接合に対する電極形成を実現で
き、ＳＢＤを用いた半導体装置の製造上効果が大きい。As explained above, according to this example, compared to the example shown in FIG. No problem arises. In other words, φ is achieved through a relatively simple process.
It is possible to realize an SBD with a low β and electrode formation for a shallow junction, which is highly effective in manufacturing semiconductor devices using the SBD.
以上述べた実施例に於いては、Ｎ型半導体基体を例にと
って説明したが、Ｐ型半導体基体にも本発明は適用でき
る。Although the embodiments described above have been explained using an N-type semiconductor substrate as an example, the present invention can also be applied to a P-type semiconductor substrate.
また、ＳＢＤの付い７’ｃＮＰＮ）ランジスタを例にと
って説明したが、これに限らず、一般的な、主表面を有
し、上記主表面に露出する第１導電型の第１の領域、上
記第１の領域との間に形成されるＰＮ接合が上記主表面
に終端するように上記第１の領域内に形成される第２導
電型の第２の領域、を少なくとも有する半導体基体と、
上記主表面に於いて上記第２の領域に低抵抗接触する第
１の電極と、上記第２の領域を除く上記主表面の少なく
とも一部にショットキー障壁が形成される様に接触する
第２−の電極とを具備する半導体装置に本発明は適用で
きる。Although the explanation is given by taking a 7'cNPN) transistor with an SBD as an example, the present invention is not limited to this. a semiconductor substrate having at least a second region of a second conductivity type formed within the first region such that a PN junction formed between the semiconductor substrate and the first region terminates at the main surface;
A first electrode in low resistance contact with the second region on the main surface, and a second electrode in contact with at least a portion of the main surface excluding the second region so as to form a Schottky barrier. The present invention can be applied to a semiconductor device including a - electrode.
以上述べた様に本発明によれば、順方向電圧降下が低く
、かつ浅いＰＮ接合の耐圧劣化が生じない半導体装置を
得ることができる。As described above, according to the present invention, it is possible to obtain a semiconductor device in which the forward voltage drop is low and the breakdown voltage of the shallow PN junction does not deteriorate.
さらに、本発明によれば、工程数が少なく経済的な半導
体装置の製造方法を得ることができる。Further, according to the present invention, it is possible to obtain an economical method of manufacturing a semiconductor device with a small number of steps.
第１図及び第２図は従来例である半導体装置の概略断面
図、第３図は本発明半導体装置の一実施例の概略断面図
、第４図は第３図の実施例の製造方法の一例を示す概略
工程図、第５図は本発明半導体装置の製造方法の一実施
例を示す概略工程図とそれに対応する概略断面図である
。
ｌ・・・Ｎ型半導体基体、２・・・Ｐ型ベース層、３・
・・Ｎ型エミツタ層、１０・・・８ＢＤ電極、１１・・
・エミッタ電極。1 and 2 are schematic sectional views of a conventional semiconductor device, FIG. 3 is a schematic sectional view of an embodiment of the semiconductor device of the present invention, and FIG. 4 is a schematic sectional view of an embodiment of the semiconductor device of the present invention. FIG. 5 is a schematic process diagram showing an example of a method for manufacturing a semiconductor device of the present invention, and a corresponding schematic sectional view. l...N-type semiconductor substrate, 2...P-type base layer, 3...
...N-type emitter layer, 10...8BD electrode, 11...
・Emitter electrode.
Claims (1)
第１の領域、上記第１の領域との間に形成されるＰＮ接
合が上記主表面に終端するように上記第１の領域内に形
成される第２導電型の第２の領域、を少なくとも有する
半導体基体と、上記主表面に於いて上記第２の領域に低
抵抗接触する第１の電極と、上記第２の領域を除く上記
主表面の少なくとも一部にショットキー障壁が形成され
る様に接触する第２の電極とを具備するものに於いて、
上記第１の電極は上記第２の電極の材料と上記半導体基
体の材料との混合物ｔ・らなることを特徴とする半導体
装置。 ２、特許請求の範囲第１項に於いて、上記半導体基体は
３ｉからなり、上記第１の電極はＡｔ−８ｉ“からなシ
、上記第２の電極はｐｕｒｅＡＡからなること′ｆ、％
徴とする半導体装置。 ３、主表面を有し、上記主表面に露出する第１導電型の
第１の領域、上記第１の領域との間に形成されるＰＮ接
合が上記主表面に終端するように上記第１の領域内に形
成される第２導電型の第２の領域、を少なくとも有する
半導体基体と、上記主表面に於いて上記第２の領域に低
抵抗接触する第１の電極と、上記第２の領域を除く上記
主表面の少なくとも一部にショットキー障壁が形成され
る様に接触する第２の電極とを具備する半導体装置の製
造方法に於いて、上記第１の電極は、上記第２の電極の
材料からなる第１層と１．上記第１層上に形成される上
記半導体基体の材料、または上記第２の電極の材料と上
記半導体基体の材料との混合物からなる第２層とを積層
して形成し、上記第２層中の半導体基体の材料が上記第
１層及び上記第２層中にほぼ均一に濃度分布し、かつ上
記第２の電極と上記半導体基体との接触部がショットキ
ー障壁を形成するに十分な温度と時間で熱処理すること
を特徴とする半導体装置の製造方法。 ４゜特許請求の範囲第３項に於いて、上記半導体基体は
Ｓｉからなり、上記第１の電極はｈｔ−ｓｉからなシ、
上記第２の電極はｐｕｒｅＡｔからなることを特徴とす
る半導体装置の製造方法。[Claims] 1. A first region of a first conductivity type having a main surface and exposed on the main surface, a PN junction formed between the first region and the main surface terminating at the main surface. a semiconductor substrate having at least a second region of a second conductivity type formed in the first region, and a first electrode in low resistance contact with the second region on the main surface. and a second electrode that contacts at least a portion of the main surface excluding the second region so as to form a Schottky barrier,
A semiconductor device, wherein the first electrode is made of a mixture of the material of the second electrode and the material of the semiconductor substrate. 2. In claim 1, the semiconductor substrate is made of 3i, the first electrode is made of At-8i", and the second electrode is made of pure AA'f,%
Semiconductor device with special characteristics. 3. a first region of a first conductivity type that has a main surface and is exposed on the main surface; a semiconductor substrate having at least a second region of a second conductivity type formed in a region of In the method for manufacturing a semiconductor device, the first electrode includes a second electrode that contacts at least a portion of the main surface excluding a region so as to form a Schottky barrier. a first layer consisting of an electrode material; 1. A second layer made of a mixture of the material of the semiconductor substrate formed on the first layer or the material of the second electrode and the material of the semiconductor substrate is laminated, and the second layer is formed in the second layer. The material of the semiconductor substrate has a substantially uniform concentration distribution in the first layer and the second layer, and the contact portion between the second electrode and the semiconductor substrate has a temperature sufficient to form a Schottky barrier. A method for manufacturing a semiconductor device, characterized in that heat treatment is performed over a period of time. 4. In claim 3, the semiconductor substrate is made of Si, and the first electrode is not made of ht-si,
A method of manufacturing a semiconductor device, wherein the second electrode is made of pure At.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21130982A JPS59101868A (en) | 1982-12-03 | 1982-12-03 | Semiconductor device having schottky barrier and low resistance contact, and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21130982A JPS59101868A (en) | 1982-12-03 | 1982-12-03 | Semiconductor device having schottky barrier and low resistance contact, and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59101868A true JPS59101868A (en) | 1984-06-12 |
Family
ID=16603802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21130982A Pending JPS59101868A (en) | 1982-12-03 | 1982-12-03 | Semiconductor device having schottky barrier and low resistance contact, and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59101868A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009134295A (en) * | 2007-11-08 | 2009-06-18 | Yamada Kogaku Kogyo Kk | Method for simultaneously viewing two or more sides of figure |
-
1982
- 1982-12-03 JP JP21130982A patent/JPS59101868A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009134295A (en) * | 2007-11-08 | 2009-06-18 | Yamada Kogaku Kogyo Kk | Method for simultaneously viewing two or more sides of figure |
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