JPS6236554U - - Google Patents

Info

Publication number
JPS6236554U
JPS6236554U JP12741085U JP12741085U JPS6236554U JP S6236554 U JPS6236554 U JP S6236554U JP 12741085 U JP12741085 U JP 12741085U JP 12741085 U JP12741085 U JP 12741085U JP S6236554 U JPS6236554 U JP S6236554U
Authority
JP
Japan
Prior art keywords
flat package
circuit
board
substrate
surface opposite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12741085U
Other languages
English (en)
Other versions
JPH0447970Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985127410U priority Critical patent/JPH0447970Y2/ja
Priority to US06/893,141 priority patent/US4722027A/en
Publication of JPS6236554U publication Critical patent/JPS6236554U/ja
Application granted granted Critical
Publication of JPH0447970Y2 publication Critical patent/JPH0447970Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の混成回路の実施例を示す組立
説明図、第２図は分解斜視図、第３図ａと第３図
ｂは外部端子とフラツトパツケージの端子の接続
部分を示す平面図、第４図はバツフアードデイレ
ーラインの回路図、第５図は従来の混成回路の説
明図である。 ３０：フラツトパツケージ、３１：基板、３２
，３４：孔、３３：溝、３５，３６：端子、３７
：外部端子、３８，３９：先端、４０：底面。

Claims (1)

    【実用新案登録請求の範囲】
  1. コイルを含む回路が構成されている基板と、該
    基板より平面積の狭い集積回路のフラツトパツケ
    ージを重ね合わせてあり、両方の回路の接続をフ
    ラツトパツケージの端子を介して行い、少くとも
    いずれかの回路に接続する外部端子を露呈させた
    状態で全体を樹脂封止してある混成回路であり、
    集積回路に接続する外部端子はその先端を、フラ
    ツトパツケージの外面に沿つて折り曲げられ基板
    と反対側の外面に延在する該フラツトパツケージ
    の端子に、該基板と反対側の外面で接続されてい
    ることを特徴とする混成回路。
JP1985127410U 1985-08-09 1985-08-21 Expired JPH0447970Y2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1985127410U JPH0447970Y2 (ja) 1985-08-21 1985-08-21
US06/893,141 US4722027A (en) 1985-08-09 1986-08-05 Hybrid circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985127410U JPH0447970Y2 (ja) 1985-08-21 1985-08-21

Publications (2)

Publication Number Publication Date
JPS6236554U true JPS6236554U (ja) 1987-03-04
JPH0447970Y2 JPH0447970Y2 (ja) 1992-11-12

Family

ID=31022134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985127410U Expired JPH0447970Y2 (ja) 1985-08-09 1985-08-21

Country Status (1)

Country Link
JP (1) JPH0447970Y2 (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780836U (ja) * 1980-10-31 1982-05-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780836U (ja) * 1980-10-31 1982-05-19

Also Published As

Publication number Publication date
JPH0447970Y2 (ja) 1992-11-12

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