JPS6232553U - - Google Patents

Info

Publication number
JPS6232553U
JPS6232553U JP12305785U JP12305785U JPS6232553U JP S6232553 U JPS6232553 U JP S6232553U JP 12305785 U JP12305785 U JP 12305785U JP 12305785 U JP12305785 U JP 12305785U JP S6232553 U JPS6232553 U JP S6232553U
Authority
JP
Japan
Prior art keywords
circuit
substrate
package
flat
flat package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12305785U
Other languages
English (en)
Other versions
JPH0447968Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985123057U priority Critical patent/JPH0447968Y2/ja
Priority to US06/893,141 priority patent/US4722027A/en
Publication of JPS6232553U publication Critical patent/JPS6232553U/ja
Application granted granted Critical
Publication of JPH0447968Y2 publication Critical patent/JPH0447968Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】
第１図は本考案の混成回路の実施例を示す組立
説明図、第２図は分解斜視図、第３図ａと第３図
ｂは外部端子とフラツトパツケージの端子の接続
部分を示す平面図、第４図はバツフアードデイレ
ーラインの回路図、第５図は従来の混成回路の説
明図である。 ３０：フラツトパツケージ、３１：基板、３２
，３４：孔、３３：溝、３５，３６：端子、３７
：外部端子、３８，３９：先端、４０：底面。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) コイルを含む回路が構成されている基板と
    、該基板より平面積の狭い集積回路のフラツトパ
    ツケージを重ね合わせてあり、両方の回路の接続
    をフラツトパツケージの端子を介して行い、少く
    ともいずれかの回路に接続する外部端子を露呈さ
    せた状態で全体を樹脂封止してある混成回路であ
    り、基板とフラツトパツケージの重ならない位置
    には該基板の回路を構成する回路素子が該フラツ
    トパツケージの横に固定してあることを特徴とす
    る混成回路。 (2) 該回路素子は基板の孔に固定してある実用
    新案登録請求の範囲第１項記載の混成回路。
JP1985123057U 1985-08-09 1985-08-09 Expired JPH0447968Y2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1985123057U JPH0447968Y2 (ja) 1985-08-09 1985-08-09
US06/893,141 US4722027A (en) 1985-08-09 1986-08-05 Hybrid circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985123057U JPH0447968Y2 (ja) 1985-08-09 1985-08-09

Publications (2)

Publication Number Publication Date
JPS6232553U true JPS6232553U (ja) 1987-02-26
JPH0447968Y2 JPH0447968Y2 (ja) 1992-11-12

Family

ID=31013813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985123057U Expired JPH0447968Y2 (ja) 1985-08-09 1985-08-09

Country Status (1)

Country Link
JP (1) JPH0447968Y2 (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780836U (ja) * 1980-10-31 1982-05-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780836U (ja) * 1980-10-31 1982-05-19

Also Published As

Publication number Publication date
JPH0447968Y2 (ja) 1992-11-12

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