JPS6235687B2 - - Google Patents
Info
- Publication number
- JPS6235687B2 JPS6235687B2 JP57109492A JP10949282A JPS6235687B2 JP S6235687 B2 JPS6235687 B2 JP S6235687B2 JP 57109492 A JP57109492 A JP 57109492A JP 10949282 A JP10949282 A JP 10949282A JP S6235687 B2 JPS6235687 B2 JP S6235687B2
- Authority
- JP
- Japan
- Prior art keywords
- register
- rounding
- carry
- operand
- registers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 23
- 238000012545 processing Methods 0.000 claims description 20
- 238000004886 process control Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49942—Significance control
- G06F7/49947—Rounding
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57109492A JPS58225436A (ja) | 1982-06-25 | 1982-06-25 | まるめ処理制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57109492A JPS58225436A (ja) | 1982-06-25 | 1982-06-25 | まるめ処理制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58225436A JPS58225436A (ja) | 1983-12-27 |
JPS6235687B2 true JPS6235687B2 (fr) | 1987-08-03 |
Family
ID=14511616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57109492A Granted JPS58225436A (ja) | 1982-06-25 | 1982-06-25 | まるめ処理制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58225436A (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6238937A (ja) * | 1985-08-13 | 1987-02-19 | Panafacom Ltd | 浮動小数点演算における保護桁処理方式 |
-
1982
- 1982-06-25 JP JP57109492A patent/JPS58225436A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS58225436A (ja) | 1983-12-27 |
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