JPS6235570A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the formation of extrafine source, drain and gate regions by forming the side wall insulating film region of a pattern sidewall as source and drain contacting regions, and the gate region in a self-aligning manner by utilizing the side wall oxide film of a polysilicon electrode. CONSTITUTION:An insulating film 8 remains by utilizing anisotropic etching on the side wall of a portion to become a gate electrode, with the film 8 as a mask an SiO2 film 9 is formed by selective oxidation. Source and drain impurity is implanted from the portion in which the film 8 of the side wall is removed to thereby form ultrafine source and drain regions 14S, 14D. Further, a gate electrode 16 allows an insulating film 12 to remain similarly on the side after forming electrodes 11S, 11D for the source and the drain, with the film 12 as a mask the pattern of a gate forming portion is etched to expose a semiconductor surface for forming a narrowed gate to form the electrode 16.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing an FET, in which a pattern side wall (side fall) O8! The IN4 film region is used as source and drain contact regions, and the gate region is formed in a self-lined manner using the sidefall S*0° film.

This makes it possible to form extremely fine source, drain, and gate regions.

[Industrial application field]

The present invention relates to a method of manufacturing a field effect semiconductor device (FET), and more particularly to a method of manufacturing a semiconductor device useful for miniaturizing the field effect semiconductor device (FET).

[Conventional technology]

A typical example of a conventional FET is shown in Figure 2.
1 is a p-8i substrate, 22 is a field insulating film, 23 is a gate oxide film (Sin), and after providing a gate electrode 25 (polysilicon) thereon, a source 26 . The ninth layer of the drain 27 is ion-implanted, and an interlayer insulating film (SIO,
(or PEG, etc.) 24, pattern the contact holes, and connect the source, drain, and gate electrodes 2.
In order to form B, 29, and 50, CA1 and the like are deposited, and then patterned to form each electrode.

In FETs, by shortening the channel length, the gain can be increased; furthermore, by reducing the parasitic capacitance, the operating speed can be improved, and MO8
In type FETs, it is effective to reduce the drain junction area.

[Problem that the invention seeks to solve]

However, as mentioned above, in the past, game) 2
5. For the formation of contact holes and extraction electrodes 28 to 50 (e, patterning by photolithography, etc. is required three times, and alignment is performed each time, so the alignment margin must be as large as possible. Therefore, there is a limit to reducing the size of the element, and there is a drawback that increasing the speed of operation is limited.

[Means for solving problems]

The present invention uses anisotropic etching to leave an insulating film 8 on the sidewall of the portion that will become the gate electrode.
), this mask is used as a selective acid, as shown in Figure 1.
(see Figure 1(A)), impurities for source and drain are introduced from the portion where the insulating film 8 on the sidewall has been removed (see Figure 1(A)).
14), thereby forming minute source and drain regions. Further, the gate electrode is also formed after forming the source and drain (two paired electrodes 11S and 11D (see FIG. 1(a))).
2 as a remaining sheet, and using this as a mask, etching the pattern of the gate formation part to expose the narrow semiconductor surface for gate formation, and forming the gate electrode on the face, the entire minute gate structure is etched. Form (direction 1).

[For production]

According to C; above, it is possible to reduce the area of the electrodes of a semiconductor device, for example, the source and drain regions of an MO8 type FET c can be made extremely narrow, and the gate length can also be miniaturized.

〔Example〕

FIG. 1 shows the manufacturing process of the MO8 type FET of the present invention, which will be explained below.

Refer to FIG. 1(A). 1 is a semiconductor substrate using a (100) plane of p-type Si, which becomes a channel region of an MO8 type transistor.

2 is a thermal oxide film (S
in, ).

Refer to Figure 1 (b) ■ 3 is the first insulating film, which was heated to 500A by applying thermal oxidation method.
Sin, which was formed to a certain degree. Besides, CVD
S i , N, film (second
6000 insulating film) 4 is formed by CVD method.
The third insulating film 5 is made of Sin and has a thickness of approximately A.

See No. 11!1 (C) ■ 6 is a resist pattern. Using this resist pattern as a mask, a 5.4.degree. 5 film is etched by RIE. After that, the resist pattern 6 is removed.

Refer to 1st cause 0■ Then, on the entire surface: SL 3 N4 of about 500OA
A film 7 (fourth insulating film) is formed.

Refer to FIG. 1 (e) ■ RIE the S z a N4 film 7 of the fourth insulation film (
Etching is performed using a reactive ion etching method to leave 5i3N48 on the side walls.

Refer to Figure 1n ■ Substrate 1 is oxidized, and the film 9 is made of about 3000 A of Sin.
form.

Refer to FIG. 1(G). 2) Etch the Si3N film on the side wall and expose the substrate Stt, which will become the source and drain contact regions.

The width of this contact region 10 is approximately 0.3 μm.

Refer to FIG. 1(b) ■ Doped polysilicon 11 (AJ doped) is formed on the entire surface. Alternatively, 11-doped silinide may be used.

Refer to FIG. 1(I). After bias sputtering or resist coating, the doped polysilicon 11 is etched by RIE (etch-back method) to planarize the surface by etching only the convex portions.

Figure 1 (See @ S'Oz film 5t is etched, and the side wall 1 of the doped polysilicon 11 is left; the SiO hot film 12 is left by RIE method (2). The width of this Si film 12 is about 0.5 μm. It is.

Refer to FIG. 1 (5) ■ Thermal oxidation (Secondly, the surface of the doped polysilicon 11 is oxidized. The formed oxide film 15 becomes an insulating film between the eyebrows. At that time, during the heating process, AJ is exposed to the contact region 10 ( Two diffused, ?-shaped source and drain regions 14S and 14
D is formed.

Refer to Fig. 1 Φ) @ Etch the area where the Si, N4 film 4 is exposed using fRIE, and then wet the underlying 5iOt 5' (1).
Etching using HF-based method.

■ After that, the gate oxide film 15 is placed on the exposed substrate Si.
A thickness of approximately Y 300 A is formed by thermal oxidation, and the gate electrode 161 is formed thereon.

According to the above steps, a fine source, drain, and gate can be formed using one mask (and alignment). The accuracy can be determined by the width of the remaining T[ on the sidewall, which can be approximately determined by the thickness of the film deposited before RIE, and can be formed sufficiently finely and precisely. Regarding the dimensions of the gate, if the width of the gate formation region (distance between source and drain electrodes) when forming source and drain contacts is 1 μm, which is within the limit of photolithography, the length of the gate formed as shown in Figure 1 (■) will be even narrower. For example, 0.4 μm (two layers can be formed).

〔Effect of the invention〕

According to the present invention, the sidewall insulating film region on the sidewall of the pattern can be used as the source and drain contact region, and the first gate region can also be formed by self-line using the oxide film of the sidewall of the polysilicon electrode. , it is possible to provide a semiconductor device with a very small number of sources, drains, and gates.

This is based on the fact that patterning using photolithography 1 only needs to be performed once, and the alignment margin can be reduced compared to the conventional method.

As a result, the parasitic capacitance of the source and drain can be reduced.
Further, it becomes possible to form a short gate length, and a high-speed, high-performance field-effect semiconductor device can be provided.

[Brief explanation of the drawing]

1111 (8) to (h are process diagrams of the embodiment of the present invention. The second factor is a cross-sectional view of the element of the conventional example. Main symbols 1...Semiconductor substrate 2...5i01 Top 3... First insulating film (Sin,) 4-@2O insulating film<si, 7v4)5...Third insulating film (Sz(Jt)8...Si remaining on the side wall
, N, (Sidewall 3i, N,) 12... Sidewall (2 remaining Sin, (Sidewall Sin,) 14S, 14D... Source, drain 16... Gate electrode special liver applicant Fujitsu Co., Ltd.

Claims (1)

[Claims] A method for manufacturing a semiconductor device, characterized by including the following steps: (a) forming a first insulating film, a second insulating film, and a third insulating film in order on a semiconductor substrate; (b) selectively removing the first to third insulating films to expose the semiconductor surface; (c) forming a fourth insulating film on the semiconductor substrate obtained in (b) above; forming and leaving the fourth insulating film on the pattern side of the first to third insulating films by anisotropic etching, (d) oxidizing the semiconductor substrate, (e) forming the fourth insulating film. etching to expose the semiconductor substrate; (f) forming a first conductive film and making electrical contact with the semiconductor substrate; (g) etching the third insulating film; (h) the above. Forming a fifth insulating film on the semiconductor substrate obtained in (g),
a step of leaving a fifth insulating film on the sidewall of the first conductive film by anisotropic etching; (i) a step of oxidizing the surface of the first conductive film; (j) a step of oxidizing the first conductive film;
and etching the second insulating film to expose the semiconductor substrate, (k) oxidizing the exposed surface of the semiconductor substrate, (l) etching a second conductive film on the oxide film formed in (k) above. The process of forming a film.